FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 149

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

4.10.2
4.10.3
4.10.3.1
4.10.4
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Dribble Bits
The LXT9785/LXT9785E device handles dribble bits in all modes. If one through four dribble bits
are received, the nibble is passed across the RMII. If five through seven dribble bits are received,
the second nibble is not sent onto the RMII bus.
Link Test
The LXT9785/LXT9785E always transmits link pulses in 10T mode. When enabled, the link test
function monitors the connection for link pulses. Once link pulses are detected, data transmission is
enabled and remains enabled as long as either the link pulses or data transmission continue. If link
pulses stop, the data transmission is disabled.
If the link test function is disabled, the LXT9785/LXT9785E transmits to the connection regardless
of detected link pulses. The link test function is disabled by setting Register bit 16.14 = 1.
Link Failure
Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this
condition occurs, the LXT9785/LXT9785E returns to the auto-negotiation phase if auto-
negotiation is enabled.
Jabber
If a transmission exceeds the jabber timer, the LXT9785/LXT9785E disables the transmit and
loopback functions and the Collision Status bit (Register bit 17.11) is set regardless of duplex. The
jabber timer, according to the IEEE standard, must be between 20 ms to 150 ms. The RMII does
not include a Jabber pin, but the MAC may read Register 1 to determine jabber status. The
LXT9785/LXT9785E automatically exits jabber mode after the unjab time expires. This function is
disabled by setting Register bit 16.10 = 1.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
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