FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 202

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
204
Table 87. Auto-Negotiation Advertisement Register (Address 4)
NOTE: Restart the auto-negotiation process whenever Register 4 is written/modified.
1. R/W = Read/Write, R = Read Only
2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
3. The default setting of Register bit 4.10 is determined by the PAUSE pin. The BGA15 package does not
4. Default settings for bits 4.5:8 are determined by CFG pins as described in
5. Pause operation is only valid for full-duplex modes.
6. If Register bit 4.13 is set to advertise a fault, Register bit 1.4 will be set.
13
Bit
4:0
15
14
12
10
11
9
8
7
6
5
the pin(s) are latched at startup or hardware reset.
have a Pause hardware configuration pin and has a default of 0.
9785E Global Hardware Configuration Settings” on page
6
Name
Remote Fault
100BASE-TX
100BASE-TX
100BASE-T4
Asymmetric
Half-Duplex
Half-Duplex
Full-Duplex
Full-Duplex
10BASE-T
10BASE-T
Next Page
Reserved
Reserved
Selector
Pause
S<4:0>
Pause
Field,
5
Description
0 = Port has no ability to send manual next pages
1 = Port has ability to send manual next pages
Note: This bit should only be set to manually control the auto-
negotiation process. It is not needed and should be cleared
for DTE Discovery.
Write as 0, ignore on Read
0 = No remote fault
1 = Remote fault
Write as 0, ignore on Read
Pause operation defined in Clause 40 and 27
0 = Port is not Pause capable
1 = Port can only send Pause
0 = Pause operation disabled
1 = Port can send and receive Pause
NOTE: Default for the BGA15 package is 0.
0 = 100BASE-T4 capability is not available
1 = 100BASE-T4 capability is available
(The LXT9785/LXT9785E does not support 100BASE-T4 but
allows this bit to be set to advertise in the auto-negotiation
sequence for 100BASE-T4 operation. An external
100BASE-T4 transceiver could be switched in if this
capability is desired.)
0 = Port is not 100BASE-TX full-duplex capable.
1 = Port is 100BASE-TX full-duplex capable
0 = Port is not 100BASE-TX half-duplex capable
1 = Port is 100BASE-TX half-duplex capable
0 = Port is not 10BASE-T full-duplex capable
1 = Port is 10BASE-T full-duplex capable
0 = Port is not 10BASE-T half-duplex capable
1 = Port is 10BASE-T half-duplex capable
<00001> = IEEE 802.3
<00010> = IEEE 802.9 ISLAN-16T
<00000> = Reserved for future auto-negotiation development
<11111> = Reserved for future auto-negotiation development
Unspecified or reserved combinations should not be
transmitted
129.
Table 42, “Intel® LXT9785/
Revision Date: August 28, 2003
Document Number: 249241
Revision Number: 007
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
1
Datasheet
LSHR
LSHR
LSHR
LSHR
LSHR
Default
00001
0
0
0
0
0
0
2,3
2,4
2,4
2,4
2,4