FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 127

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

4.5.5
4.6
4.6.1
4.6.1.1
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 42. Intel
Intel recommends that a minimum recovery time be allowed after bringing up a port from software
or hardware reset. The recovery times are specified in
Power-Up Timing Parameters” on page 198
Hardware Configuration Settings
The LXT9785/LXT9785E provides a hardware option to set the initial device configuration. The
hardware option uses three Global CFG pins that provide control for all ports (see
Link Establishment
Auto-Negotiation
The LXT9785/LXT9785E attempts to auto-negotiate with its link partner by sending Fast Link
Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 µs apart. Odd link pulses
(clock pulses) are always present. Even link pulses (data pulses) may also be present or absent to
indicate a “1” or a “0”. Each FLP burst exchanges 16 bits of data, referred to as a “page”. All
devices that support auto-negotiation must implement the “Base Page”, defined by IEEE 802.3
(registers 4 and 5). The LXT9785/LXT9785E also supports the optional “Next Page” function
(registers 7 and 8).
Base Page Exchange
By exchanging Base Pages, the LXT9785/LXT9785E and its link partner communicate their
capabilities to each other. Both sides must receive at least three identical base pages for negotiation
to proceed. Each side finds their highest common capabilities, exchange more pages, and agree on
the operating state of the line.
AutoNeg
Disabled
1. Refer to
Enabled
Table 17, “Intel® LXT9785/LXT9785E Receive FIFO Depth Considerations” on page 50 Table 24, “Intel®
LXT9785/LXT9785E RMII Signal Descriptions – BGA23” on page 82
LXT9785E Receive FIFO Depth Configurations” on page
Descriptions” on page 109
®
LXT9785/9785E Global Hardware Configuration Settings
Desired Mode
Table 5, “Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP” on page 36
Speed
10/100
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
100
100
10
Full/Half
Full/Half
Duplex
Half
Half
Half
Half
Full
Full
for CFG pin assignments.
High
High
High
High
Low
Low
Low
Low
1
Pin Settings
CFG
High
High
High
High
Low
Low
Low
Low
2
1
High
High
High
High
Low
Low
Low
Low
3
0.12
97, and
Table 80, “Intel® LXT9785/LXT9785E
0
1
0.13
Table 39, “Intel® LXT9785 BGA15 Signal
Resulting Register Bit Values
0
1
1
1
1
1
through
0.8
0
1
0
1
0
0
0
0
Table 36, “Intel® LXT9785/
4.8
0
1
0
1
Auto-Negotiation
Advertisement
4.7
1
1
1
1
Table
N/A
through
4.6
0
0
1
42).
4.5
129
0
1
1