FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 188

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FWIXEPAD0SE001

Manufacturer Part Number
FWIXEPAD0SE001
Description
Advanced 8-Port 10/100 Mbps PHY Transceivers
Manufacturer
INTEL [Intel Corporation]
Datasheet
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
190
Figure 51. Intel
Table 72. Intel
RxData<1:0>, CRS_DV, RXER setup to REFCLK
rising edge
RxData<1:0>, CRS_DV, RXER hold from REFCLK
rising edge
Receive start of /J/ to CRS_DV asserted
Receive start of /T/ to CRS_DV de-asserted
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
3. Values and conditions from RMII Specification, Rev. 1.2.
testing.
100BASE-TX or 100BASE-FX).
®
®
LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters
RxData[1:0]
LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing
default configuration of 00 (32 bits of initial fill).
CRS_DV
REFCLK
3
3
TPFI
Parameter
t
3
Sym
t1
t2
t3
t4
t
1
Min
t
4
2
2
Typ
16
20
t
4
1
Max
14
14
21
27
Revision Date: August 28, 2003
Document Number: 249241
Units
BT
BT
ns
ns
Revision Number: 007
2
2
Conditions
Datasheet
Test

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