FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 135

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

4.7.6
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Figure 19. Intel
Table 44. Intel
Source Synchronous-Serial Media Independent Interface
Some system designs require the PHY to be placed between 3 to 12 inches away from the MAC. A
new Source Synchronous-Serial Media Independent Interface (SS-SMII) definition has been added
because of this requirement. To provide a source synchronous interface between the PHY and
MAC, the PHY must drive the RxCLK and the RxSYNC signals to the MAC. Also, the MAC must
drive the TxCLK and the TxSYNC signal to the PHY. The REFCLK is also needed to synchronize
the data to the PHY’s core clock domain. TxData is clocked in using TxCLK and then
synchronized to REFCLK and transmitted to the twisted-pair. The RxData is synchronized to the
RxCLK. See
CRS
RxDV
RxER
(RxData0)
SPEED
(RxData1)
DUPLEX
(RxData2)
LINK
(RxData3)
JABBER
(RxData4)
VALID
(RxData5)
False Carrier
(RxData6)
RxData7
1. Both RxData0 and RxData5 bits are valid in the segment immediately following a frame, and remain valid
CLOCK
RxSYNC
until the first data segment of the next frame begins.
®
Signal
RX
®
LXT9785/LXT9785E RX Status Encoding Bit Definitions
LXT9785/LXT9785E Serial MII Receive Synchronization
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 23 on page
Carrier Sense - identical to MII, except that it is not an asynchronous signal.
Receive Data Valid - identical to MII. When RX_DV = 0, status
information is transmitted to the MAC. When RX_DV = 1,
received data is transmitted to the MAC.
Inter-frame status bit RxData0 indicates whether or not the
PHY detected an error somewhere in the previous frame.
Inter-frame status bit RxData1 indicates port operating speed.
Inter-frame status bit RxData2 indicates port duplex condition.
Inter-frame status bit RxData3 indicates port link status.
Inter-frame status bit RxData4 indicates port jabber status.
Inter-frame status bit RxData5 conveys the validity of the upper
nibble of the last byte of the previous frame
Inter-frame status bit RxData6 indicates whether or not the
PHY has detected a false carrier event.
This bit is set to 1.
CRS
RX_DV
141.
RXD0
RXER
RXD1
Speed
RXD2
Duplex
Definition
RXD3
Link
RXD4
J abber
RXD5
Valid
0 = Status Byte
1 = Valid Data Byte
0 = No Error
1 = Error
0 = 10 Mbps
1 = 100 Mbps
0 = Half-duplex
1 = Full-duplex
0 = Down
1 = Up
0 = OK
1 = Error
0 = Invalid
1 = Valid
0 = No FC detected
1 = FC detected
1 = Always
RXD6
FCE
RXD7
RXD7
CRS
137