FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 122

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.3.10
4.3.11
124
Figure 12. Intel
Global Hardware Control Interface
The LXT9785/LXT9785E provides a Hardware Control Interface for applications where the
MDIO is not desired. Refer to
FIFO Initial Fill Values
The FIFO initial fill value sets the number of bits required to be written into the FIFO before the
process of reading the packet out of the FIFO is started. The read operation is aligned on nibble
boundaries because the FIFO is one nibble wide. The read clock on the RMII and SMII interfaces
may occur any time within the next available nibble. Therefore, the effective size of the FIFO is
one nibble less than the selected size.
Large initial fill FIFO settings alter both the data-path latency and the InterFrame Gap (IFG) output
on the RMII and SMII interfaces. The latency values are increased or decreased depending on the
number of bits the FIFO size is increased or decreased. The IFG may decrease up to twice the size
of the initial fill FIFO setting. When the following three conditions are met, the IPG on the RMII
and SMII interfaces may become nonexistent between packets, effectively concatenating the
packets into one long corrupted packet:
The concatenation of the packets is flagged by the MAC as a CRC error and possibly an oversized
packet depending upon the length indication capabilities of the MAC. The possibility of packet
concatenation can be minimized on the RMII interface by setting the initial fill FIFO Register bits
18.15:14 to 01. The FIFO setting bits should be set to 10 for the SMII interfaces.
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Interrupt (Event) Status Register is cleared on read.
X = Any Interrupt capabi lity
Force Interrupt
Event X Enable Reg
Event X Status Reg
Auto-negotiation complete.
Speed status change.
Duplex status change.
Link status change.
Isolate status change.
The frequency difference between the link partner and the local LXT9895 device exceed
200 ppm (the IEEE standard requirement).
Jumbo packets (8192 byte packets or longer) are used.
Packets on the wire occur with minimum Inter-Packet Gap (IPG) of 96 bit times.
®
LXT9785/LXT9785E Interrupt Logic
Per Event
. .
.
AND
“Initialization” on page 126
Interrupt Enable
OR
AND
for additional details.
Per port
. . .
Revision Date: August 28, 2003
Port
Combine
Logic
Document Number: 249241
Revision Number: 007
Interrupt Pin
Datasheet