FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 35

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 5.
Intel
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
PQFP
203
204
202
34
35
22
23
13
14
60
51
41
33
21
12
55
54
46
45
37
36
28
27
16
15
Designation
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
resistors are also disabled when the output is enabled.
Power-Down modes and during H/W reset.
4
5
3
8
7
®
Pin-Ball
LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet 2 of 3)
PBGA
D13,
C14,
A11,
B13,
E14,
B11,
A14,
A13,
B14,
C10
A16
C16
D16
C12
B15
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
D11
D8,
E3,
B2,
C6,
A7,
C2,
A3,
B6,
D9,
A6
B1
B4
C7
B9
RxData0_0
RxData0_1
RxData1_0
RxData1_1
RxData2_0
RxData2_1
RxData3_0
RxData3_1
RxData4_0
RxData4_1
RxData5_0
RxData5_1
TxData3_0
TxData3_1
TxData4_0
TxData4_1
TxData5_0
TxData5_1
TxData6_0
TxData6_1
TxData7_0
TxData7_1
Symbol
TxEN0
TxEN1
TxEN2
TxEN3
TxEN4
TxEN5
TxEN6
TxEN7
O, TS, ID
O, TS, ID
O, TS, ID
O, TS, ID
O, TS, ID
O, TS, ID
Type
O, TS
O, TS
O, TS
O, TS
O, TS
O, TS
I, ID
I, ID
I, ID
I, ID
I, ID
I, ID
1
Signal Description
Transmit Data - Port 3.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 3 are clocked in synchronously to REFCLK.
Transmit Data - Port 4.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 4 are clocked in synchronously to REFCLK.
Transmit Data - Port 5.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 5 are clocked in synchronously to REFCLK.
Transmit Data - Port 6.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 6 are clocked in synchronously to REFCLK.
Transmit Data - Port 7.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 7 are clocked in synchronously to REFCLK.
Transmit Enable - Ports 0-7.
Active High input enables respective port transmitter.
This signal must be synchronous to the REFCLK.
Receive Data - Port 0.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 1.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 2.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 3.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 4.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 5.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
2,3
37