FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 120

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
122
Figure 9. Intel
Figure 10. Intel
Note: The BGA15 package does not support the MDDIS pin.
physical connection, a specific protocol that runs across the connection, and an internal set of
addressable registers. Some registers are required and their functions are defined by the IEEE
802.3 specification. Additional registers allow for expanded functionality. Specific bits in the
registers are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is
the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs are
completely disabled. The Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used.
The timing for the MDIO Interface is shown in
Timing Parameters” on page
LXT9785/LXT9785E Management Interface Read Frame Structure” on page 122 and Figure 10,
“Intel® LXT9785/LXT9785E Management Interface Write Frame Structure” on page
The protocol allows one controller to communicate with multiple LXT9785/LXT9785E chips. Pins
ADD_<4:0> determine the base address. Each port adds its port number to the base address to
obtain its port address as shown in
The BGA15 package uses a similar scheme where the ADD_[2:0] bits internally set to 0 and the
ADD_[4:3] bits are used to select from four base addresses (0x00000b, 0x01000b, 0x10000b, or
0x11000b.
(Write)
MDIO
(Read)
MDC
MDIO
MDC
High Z
®
®
Idle
LXT9785/LXT9785E Management Interface Read Frame Structure
LXT9785/LXT9785E Management Interface Write Frame Structure
Preamble
32 "1"s
Preamble
32 "1"s
0
0
ST
ST
1
1
1
0
Op Code
Op Code
197. MDIO read and write cycles are shown in
0
1
Write
Figure
A4
A4
PHY Address
PHY Address
A3
A3
11.
A0
A0
Write
Table 79, “Intel® LXT9785/LXT9785E MDIO
R4
R4
Register Address
Register Address
R3
R3
R0
R0
Z
Around
1
Turn
Around
Turn
0
0
D15
D15
D15
D14
Revision Date: August 28, 2003
Data
Read
D14
D14
Document Number: 249241
D1
Figure 9, “Intel®
Data
D1
Revision Number: 007
D1
D0
D0
122.
Datasheet
Idle
Idle