MC9S08JM16CGTE FREESCALE [Freescale Semiconductor, Inc], MC9S08JM16CGTE Datasheet - Page 147

• Manufacturer Part Number: MC9S08JM16CGTE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

10.4
The ADC module is disabled during reset or when the ADCH bits are all high. The module is idle when a
conversion has completed and another conversion has not been initiated. When idle, the module is in its
lowest power state.
The ADC can perform an analog-to-digital conversion on any of the software selectable channels. In 12-bit
and 10-bit mode, the selected channel voltage is converted by a successive approximation algorithm into
a 12-bit digital result. In 8-bit mode, the selected channel voltage is converted by a successive
approximation algorithm into a 9-bit digital result.
When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL). In
10-bit mode, the result is rounded to 10 bits and placed in the data registers (ADCRH and ADCRL). In
8-bit mode, the result is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO)
is then set and an interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1).
The ADC module has the capability of automatically comparing the result of a conversion with the
contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates
with any of the conversion modes and configurations.
10.4.1
One of four clock sources can be selected as the clock source for the ADC module. This clock source is
then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is
selected from one of the following sources by means of the ADICLK bits.
Freescale Semiconductor
ADPC19
ADPC18
ADPC17
ADPC16
Field
•
•
•
3
2
1
0
The bus clock, which is equal to the frequency at which software is executed. This is the default
selection following reset.
The bus clock divided by two. For higher bus clock rates, this allows a maximum divide by 16 of
the bus clock.
ALTCLK, as defined for this MCU (See module section introduction).
Functional Description
ADC Pin Control 19. ADPC19 controls the pin associated with channel AD19.
0 AD19 pin I/O control enabled
1 AD19 pin I/O control disabled
ADC Pin Control 18. ADPC18 controls the pin associated with channel AD18.
0 AD18 pin I/O control enabled
1 AD18 pin I/O control disabled
ADC Pin Control 17. ADPC17 controls the pin associated with channel AD17.
0 AD17 pin I/O control enabled
1 AD17 pin I/O control disabled
ADC Pin Control 16. ADPC16 controls the pin associated with channel AD16.
0 AD16 pin I/O control enabled
1 AD16 pin I/O control disabled
Clock Select and Divide Control
Table 10-12. APCTL3 Register Field Descriptions (continued)
MC9S08JM16 Series Data Sheet, Rev. 2
Description
Analog-to-Digital Converter (S08ADC12V1)
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