MC9S08JM16CGTE FREESCALE [Freescale Semiconductor, Inc], MC9S08JM16CGTE Datasheet - Page 168

• Manufacturer Part Number: MC9S08JM16CGTE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Inter-Integrated Circuit (S08IICV2)
In slave mode, the same functions are available after an address match has occurred.
The TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for
the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is
desired, reading the IICD does not initiate the receive.
Reading the IICD returns the last byte received while the IIC is configured in master receive or slave
receive modes. The IICD does not reflect every byte transmitted on the IIC bus, nor can software verify
that a byte has been written to the IICD correctly by reading it back.
In master transmit mode, the first byte of data written to IICD following assertion of MST is used for the
address transfer and must comprise of the calling address (in bit 7 to bit 1) concatenated with the required
R/W bit (in position bit 0).
11.3.6
168
AD[10:8]
Reset
GCAEN
ADEXT
Field
DATA
Field
7–0
2–0
7
6
W
R
GCAEN
IIC Control Register 2 (IICC2)
Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
General Call Address Enable. The GCAEN bit enables or disables general call address.
0 General call address is disabled
1 General call address is enabled
Address Extension. The ADEXT bit controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address
scheme. This field is only valid when the ADEXT bit is set.
0
7
When transitioning out of master receive mode, the IIC mode must be
switched before reading the IICD register to prevent an inadvertent
initiation of a master receive data transfer.
= Unimplemented or Reserved
ADEXT
0
6
Figure 11-8. IIC Control Register (IICC2)
Table 11-8. IICC2 Field Descriptions
MC9S08JM16 Series Data Sheet, Rev. 2
Table 11-7. IICD Field Descriptions
0
0
5
NOTE
0
0
4
Description
Description
3
0
0
AD10
0
2
Freescale Semiconductor
AD9
0
1
AD8
0
0