MC9S08JM16CGTE FREESCALE [Freescale Semiconductor, Inc], MC9S08JM16CGTE Datasheet - Page 187

• Manufacturer Part Number: MC9S08JM16CGTE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
Field
CME
VDIV
3:0
5
Clock Monitor Enable — Determines if a reset request is made following a loss of external clock indication. The
CME bit must only be set to a logic 1 when either the MCG is in an operational mode that uses the external clock
(FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2 register).
Whenever the CME bit is set to a logic 1, the value of the RANGE bit in the MCGC2 register must not be changed.
0 Clock monitor is disabled.
1 Generate a reset request on loss of external clock.
VCO Divider — Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the
multiplication factor (M) applied to the reference clock frequency.
0000 Encoding 0 — Reserved.
0001 Encoding 1 — Multiply by 4.
0010 Encoding 2 — Multiply by 8.
0011 Encoding 3 — Multiply by 12.
0100 Encoding 4 — Multiply by 16.
0101 Encoding 5 — Multiply by 20.
0110 Encoding 6 — Multiply by 24.
0111 Encoding 7 — Multiply by 28.
1000 Encoding 8 — Multiply by 32.
1001 Encoding 9 — Multiply by 36.
1010 Encoding 10 — Multiply by 40.
1011 Encoding 11 — Reserved (default to M=40).
11xx Encoding 12-15 — Reserved (default to M=40).
Table 12-5. MCG PLL Register Field Descriptions (continued)
MC9S08JM16 Series Data Sheet, Rev. 2
Description
Multi-Purpose Clock Generator (S08MCGV1)
187