MC9S08JM16CGTE FREESCALE [Freescale Semiconductor, Inc], MC9S08JM16CGTE Datasheet - Page 156

• Manufacturer Part Number: MC9S08JM16CGTE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Analog-to-Digital Converter (S08ADC12V1)
than V
straight-line linear conversions. There is a brief current associated with V
capacitor is charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or
23.5 cycles when ADLSMP is high.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins must not be
transitioning during conversions.
10.6.2
Several sources of error exist for A/D conversions. These are discussed in the following sections.
10.6.2.1
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling
to within 1/4
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (R
below 2 kΩ.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the
sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
10.6.2.2
Leakage on the I/O pins can cause conversion error if the external analog source resistance (R
If this error cannot be tolerated by the application, keep R
1/4
10.6.2.3
System noise that occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
156
LSB
•
•
•
•
•
REFL
leakage error (N = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode).
There is a 0.1 μF low-ESR capacitor from V
There is a 0.1 μF low-ESR capacitor from V
If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from
V
V
Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to ADCSC1 with a wait
— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces V
DDAD
SSAD
instruction or stop instruction.
noise but increases effective conversion time due to stop recovery.
, the converter circuit converts it to 0x000. Input voltages between V
Sources of Error
LSB
Sampling Error
Pin Leakage Error
Noise-Induced Errors
(and V
to V
(at 12-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
SSAD
REFL
.
, if connected) is connected to V
MC9S08JM16 Series Data Sheet, Rev. 2
REFH
DDAD
AS
to V
to V
SS
lower than V
at a quiet point in the ground plane.
REFL
SSAD
.
.
DDAD
REFL
when the sampling
/ (2
REFH
N
*I
Freescale Semiconductor
LEAK
and V
) for less than
REFL
AS
AS
) is kept
) is high.
are
DD