MC9S08JM16CGTE FREESCALE [Freescale Semiconductor, Inc], MC9S08JM16CGTE Datasheet - Page 96

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MC9S08JM16CGTE

Manufacturer Part Number
MC9S08JM16CGTE
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Chapter 6 Parallel Input/Output
6.5.14
In addition to the I/O control, port G pins are controlled by the registers listed below.
96
PTGPEn
PTGSEn
Reset
Reset
Field
Field
5:0
5:0
W
W
R
R
Port G Pin Control Registers (PTGPE, PTGSE, PTGDS)
Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port G bit n.
1 Internal pullup device enabled for port G bit n.
Output Slew Rate Control Enable for Port G Bits— Each of these control bits determine whether output slew
rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
0
0
7
7
Figure 6-35. Output Slew Rate Control Enable for Port G Bits (PTGSE)
Figure 6-34. Internal Pullup Enable for Port G Bits (PTGPE)
0
0
6
6
Table 6-34. PTGSE Register Field Descriptions
Table 6-33. PTGPE Register Field Descriptions
PTGPE5
PTGSE5
MC9S08JM16 Series Data Sheet, Rev. 2
0
1
5
5
PTGPE4
PTGSE4
0
1
4
4
Description
Description
PTGPE3
PTGSE3
3
0
3
1
PTGPE2
PTGSE2
0
1
2
2
PTGPE1
PTGSE1
Freescale Semiconductor
0
1
1
1
PTGPE0
PTGSE0
0
1
0
0

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