MC9S08JM16CGTE FREESCALE [Freescale Semiconductor, Inc], MC9S08JM16CGTE Datasheet - Page 67

• Manufacturer Part Number: MC9S08JM16CGTE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

5.6
The MC9S08JM16 series includes a system to protect memory contents against low voltage conditions and
control MCU system states during supply voltage variations. The system is composed of a power-on reset
(POR) circuit and an LVD circuit with a user selectable trip voltage, either high (V
The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected by LVDV in
SPMSC2. The LVD is disabled upon entering any of the stop modes unless the LVDSE bit is set. If LVDSE
and LVDE are both set, then the MCU cannot enter stop2, and the current consumption in stop3 with the
LVD enabled will be greater.
5.6.1
When power is initially applied to the MCU, or when the supply voltage drops below the V
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in
reset until the supply has risen above the V
following a POR.
5.6.2
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
an LVD reset or POR.
Freescale Semiconductor
Number
Vector
5
4
3
2
1
0
Low-Voltage Detect (LVD) System
Power-On Reset Operation
LVD Reset Operation
0xFFFC:FFFD
0xFFFA:FFFB
0xFFFE:FFFF
0xFFF4:FFF5
0xFFF6:FFF7
0xFFF8:FFF9
(High/Low)
Address
Table 5-1. Vector Summary (from Lowest to Highest Priority) (continued)
Vector Name
Vreset
Vspi1
Vswi
Vlvd
Virq
Vlol
MC9S08JM16 Series Data Sheet, Rev. 2
LVDL
Module
System
System
control
control
MCG
SPI1
Core
IRQ
level. Both the POR bit and the LVD bit in SRS are set
SWI Instruction
Illegal address
Illegal opcode
RESET pin
Source
SPTEF
MODF
SPMF
BDFR
SPRF
LOLS
LVDF
IRQF
COP
POR
LOC
LVD
Chapter 5 Resets, Interrupts, and System Configuration
Enable
SPMIE
LVDRE
SPTIE
LOLIE
LVDIE
IRQIE
COPE
SPIE
SPIE
ILOP
ILAD
CME
POR
—
—
LVDH
Low-voltage detect
Low-voltage detect
Software interrupt
BDM-forced reset
MCG loss of lock
Watchdog timer
Power-on-reset
Illegal address
Illegal opcode
Loss of clock
Description
External pin
) or low (V
IRQ pin
SPI1
POR
level, the
LVDL
67
).