MC9S08JM16CGTE FREESCALE [Freescale Semiconductor, Inc], MC9S08JM16CGTE Datasheet - Page 33

• Manufacturer Part Number: MC9S08JM16CGTE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

3.6
One of two stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set. In
any stop mode, the bus and CPU clocks are halted. The MCG module can be configured to leave the
reference clocks running. See
information.
HCS08 devises that are designed for low-voltage operation (1.8 to 3.6 V) support stop1 mode. The
MC9S08JM16 series of MCUs do not support stop1 mode.
Table 3-1
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1
Stop3 mode is entered by executing a STOP instruction under the conditions shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
clock (RTC) interrupt, the USB resume interrupt, LVD, ADC, IRQ, KBI, SCI or the ACMP.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.1.1
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the
user attempts to enter stop2 with the LVD enabled for stop, the MCU will enter stop3 instead.
For the ADC to operate the LVD must be left enabled when entering stop3.
Freescale Semiconductor
1
2
STOPE
Stop Modes
ENBDM is located in the BDCSCR which is only accessible through BDC commands, see
“BDC Status and Control Register
When in stop3 mode with BDM enabled, The S
enabled.
shows all of the control bits that affect stop mode selection and the mode selected under various
0
1
1
1
1
Stop3 Mode
LVD Enabled in Stop Mode
ENBDM
x
1
0
0
0
1
Both bits must be 1
LVDE
Chapter 12, “Multi-Purpose Clock Generator
Either bit a 0
Either bit a 0
MC9S08JM16 Series Data Sheet, Rev. 2
x
x
Table 3-1. Stop Mode Selection
LVDSE
(BDCSCR).”
PPDC
0
1
x
x
x
IDD
will be near R
Stop modes disabled; illegal opcode reset if STOP
instruction executed
Stop3 with BDM enabled
Stop3 with voltage regulator active
Stop3
Stop2
IDD
levels because internal clocks are
Stop Mode
2
(S08MCGV1),” for more
Chapter 3 Modes of Operation
Section 18.4.1.1,
Table
3-1. The
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