MC9S08JM16CGTE FREESCALE [Freescale Semiconductor, Inc], MC9S08JM16CGTE Datasheet - Page 82

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MC9S08JM16CGTE

Manufacturer Part Number
MC9S08JM16CGTE
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Chapter 6 Parallel Input/Output
6.5.3
Port B parallel I/O function is controlled by the registers listed below.
82
PTBDD[5:0]
PTADS[5,0]
PTBD[5:0]
Reset
Reset
Field
Field
Field
5,0
5:0
5:0
W
W
R
R
Port B I/O Registers (PTBD and PTBDD)
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
0
0
7
7
0
0
6
6
Table 6-7. PTBDD Register Field Descriptions
Table 6-5. PTASE Register Field Descriptions
Figure 6-8. Data Direction for Port B (PTBDD)
Table 6-6. PTBD Register Field Descriptions
Figure 6-7. Port B Data Register (PTBD)
PTBDD5
MC9S08JM16 Series Data Sheet, Rev. 2
PTBD5
0
0
5
5
PTBDD4
PTBD4
0
0
4
4
Description
Description
Description
PTBDD3
PTBD3
3
0
3
0
PTBDD2
PTBD2
0
0
2
2
PTBDD1
Freescale Semiconductor
PTBD1
0
0
1
1
PTBDD0
PTBD0
0
0
0
0

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