AX88780_07 ASIX [ASIX Electronics Corporation], AX88780_07 Datasheet - Page 18

• Manufacturer Part Number: AX88780_07
• Description: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

4.1 CMD--Command Register
Offset Address = 0xFC00
31:16
15
14
13:10
9
8
7
6
5:1
0
4.2 IMR--Interrupt Mask Register
Offset Address = 0xFC04
31:6
5
4
3
Field
Field
RXVLAN
TXVLAN
RXEN
TXEN
INTMOD
WAKEMOD
-
PHYMASK
PRIM
PTIM
Name
Name
-
-
-
-
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
Type Default
All 0’s
0
0
0
All 0’s
0
0
All 0’s
1
0
0
0
All 0’s
1
Default
Reserved
RX VLAN indicator
Driver enables this bit to indicate AX88780 that the received packet will
include 4 bytes VLAN tag; AX88780 will skip 4 bytes when it calculates the
checksum of IP, TCP or UDP packet.
1 = enable
0 = disable
TX VLAN indicator
Driver enables this bit to indicate AX88780 that the transmitted packet will
include 4 bytes VLAN tag; AX88780 will skip 4 bytes when it calculates the
checksum of IP, TCP or UDP packet.
1 = enable
0 = disable
Reserved
RX Function Enable
When this bit is enabled, MAC starts to receive packets.
1 = enable
0 = disable
TX Function Enable
When this bit is enabled, MAC could start to transmit packet to Ethernet.
1 = enable
0 = disable
Reserved
Interrupt Active Mode
Driver sets this bit to indicate AX88780 that the interrupt of system is
activated high or low.
1: Active high
0: Active low
Reserved
WAKEUP pin polarity
Driver sets this bit to indicate AX88780 that the polarity of system wake-up
signal is activated high or low.
1: Active high
0: Active low
Reserved
PHY interrupt Mask
When this bit is enabled, an interrupt request from PHY set in bit 5 of
Interrupt Status Register will make AX88780 to issue an interrupt to host.
1 = enable
0 = disable
Packet Received Interrupt Mask
When this bit is enabled, a received interrupt request set in bit 4 of Interrupt
Status Register will make AX88780 to issue an interrupt to host.
1 = enable
0 = disable
Packet Transmitted Interrupt Mask
When this bit is enabled, a transmitted interrupt request set in bit 3 of Interrupt
Status Register will make AX88780 issue an interrupt to host.
Default = 0x0000_0201
Default = 0x0000_0000
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Description
Description
ASIX ELECTRONICS CORPORATION
AX88780