AX88780_07 ASIX [ASIX Electronics Corporation], AX88780_07 Datasheet - Page 19

• Manufacturer Part Number: AX88780_07
• Description: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

2
1
0
4.3 ISR--Interrupt Status Register
Offset Address = 0xFC08
Field
31:6
5
4
3
2
1
0
Name
PHYIG
RPIG
FTPI
WDTEI
RXFULI
DOGIM
RXFULIM
-
-
-
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
All 0’s
0
0
0
0
0
Default
0
0
0
0
Description
Reserved
PHY Interrupt Generation
If this bit is set to ‘1’ it means there is an interrupt request from PHY. MAC will
forward this interrupt to system. Meantime driver should poll PHY and adopt
proper procedure. Write ‘1’ to this bit to clear this request status.
1 = have interrupt request
0 = no interrupt request
Receive Packet Interrupt Generation
If this bit is set to ‘1’ it means MAC receives a packet or (packets) from cable.
The packet is kept in RX buffer. Write ‘1’ to this bit to clear this request status.
1 = have received packet
0 = no received packet
Finish Transmitting Packet Interrupt
If this bit is set to ‘1’ it means MAC had transmitted packet to cable. Write ‘1’ to
this bit to clear this request status.
1 = finish transmitting
0 = none
Reserved
Watch Dog Timer Expired Interrupt
If this bit is set to ‘1’ it means the WATCH DOG timer is expired. AX88780 will
issue an interrupt to host. Write ‘1’ to this bit to clear this request status. The
expired duration can refer to DOGTHD0 and DOGTHD1 registers.
1 = timer expired happens
0 = none
RX Buffer Full Interrupt
If this bit is set to ‘1’ it means RX buffer is full and no more packets will be
received until packets are read out. Write ‘1’ to this bit to clear this request status.
1 = RX buffer full
0 = None
Default = 0x0000_0000
1 = enable
0 = disable
Reserved
Watch Dog Timer Interrupt Mask
When this bit is enabled, a watch dog timer expired interrupt request set in
bit1 of Interrupt Status Register will make AX88780 to issue an interrupt to
host
1 = enable
0 = disable
Rx Buffer Full Interrupt Mask
When this bit is enabled, a RX buffer full interrupt request set in bit 0 of
Interrupt Status Register will make AX88780 to issue an interrupt to host.
1 = enable
0 = disable
19
ASIX ELECTRONICS CORPORATION
AX88780