AX88780_07 ASIX [ASIX Electronics Corporation], AX88780_07 Datasheet - Page 28

• Manufacturer Part Number: AX88780_07
• Description: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

2
1
0
4.29 MDIOCTRL--MDIO Control Register
Offset Address = 0xFC84
Field
31:16
15
14
12:8
7:5
4:0
4.30 MDIODP--MDIO Data Port Register
Offset Address = 0xFC88
Field
31:16
15:0
Name
WTEN
RDEN
PHYCRIDX R/W
PHYID
Name
MDPORT R/W
UNICAST
MULTICAST
RXANY
-
-
-
Type
R
Type
R
R/W
R/W
R/W
R
Default
All 0’s
All 0’s
R/W
R/W
R/W
Default
All 0’s
0
0
00000
000
00000
1
0
0
Reserved
PHY Data Port
To or from internal PHY data is put in this field.
Reserved
Write Enable.
Driver enables this bit to issue a write cycle to PHY, it will be cleared when
finished the write cycle
1 = enable
0 = disable
Read Enable.
Driver enables this bit to issue a read cycle to PHY. This bit will be cleared when
finished the read cycle
1 = enable
0 = disable
PHY Register Index
If driver wants to access PHY, set this field to define the internal register index of
PHY.
Reserved
PHY ID
If driver wants to access PHY, set this field to define the address (ID) of PHY.
The address of internal PHY is fixed to 0x10
Default = 0x0000_0000
Default = 0x0000_0000
28
0 = disable
Receive Directed Packet.
If this bit is enabled, AX88780 will compare the destination address
field of received packet with the address of MAC (refer to MACID0,
MACID1, MACID2). When it is matched and good CRC, the packet
will be passed to driver. Otherwise it will be dropped.
1 = enable
0 = disable
Receive all Multicast Packets.
If this bit is enabled, any multicast packet (good CRC) will be received
and passed to driver.
1 = enable
0 = disable
Receive Anything.
If this bit is enabled, any packet whether it is good or fail will be
received and passed to driver.
1 = enable
0 = disable
Description
Description
ASIX ELECTRONICS CORPORATION
AX88780