S29GL256P10FFI022 Spansion, S29GL256P10FFI022 Datasheet - Page 32

• Manufacturer Part Number: S29GL256P10FFI022
• Description: Flash 256M, 3V, 110ns Parallel NOR Flash
• Manufacturer: Spansion

Specifications of S29GL256P10FFI022

• Rohs: yes
• Data Bus Width: 16 bit
• Memory Type: NOR Flash
• Memory Size: 256 Mbit
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: CFI
• Access Time: 100 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 110 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-64
• Organization: 128 KB x 1024

32
7.7.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically preprograms and verifies the entire memory to an all zero data pattern prior to
electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not
required to provide any controls or timings during these operations. The Command Definitions
shows the address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that sector returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer
to “Write Operation Status” for information on these status bits.
The Unlock Bypass feature allows the host system to send program commands to the Flash device without
first writing unlock cycles within the command sequence. See
function.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that sector has returned to reading array data, to ensure the entire array is properly erased.
Software Functions and Sample Code
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level
Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory
software development guidelines.
Cycle
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
1
2
3
4
5
6
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0010;
Chip Erase Command
Setup Command
Description
Unlock
Unlock
Unlock
Unlock
S29GL-P MirrorBit
*/
(LLD Function = lld_ChipEraseCmd)
Operation
Table 7.9 Chip Erase
D a t a
Write
Write
Write
Write
Write
Write
®
Flash Family
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
/* write chip erase command
S h e e t
Table 12.1 on page
Byte Address
Base + AAAh
Base + AAAh
Base + AAAh
Base + AAAh
Base + 555h
Base + 555h
Section 7.7.8
Word Address
S29GL-P_00_A14 October 22, 2012
69. These commands invoke the
Base + 2AAh
Base + 2AAh
Base + 555h
Base + 555h
Base + 555h
Base + 555h
for details on the Unlock Bypass
*/
*/
*/
*/
on page 68
00AAh
00AAh
0055h
0080h
0055h
0010h
Data