S29GL256P10FFI022 Spansion, S29GL256P10FFI022 Datasheet - Page 35

• Manufacturer Part Number: S29GL256P10FFI022
• Description: Flash 256M, 3V, 110ns Parallel NOR Flash
• Manufacturer: Spansion

Specifications of S29GL256P10FFI022

• Rohs: yes
• Data Bus Width: 16 bit
• Memory Type: NOR Flash
• Memory Size: 256 Mbit
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: CFI
• Access Time: 100 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 110 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-64
• Organization: 128 KB x 1024

October 22, 2012 S29GL-P_00_A14
7.7.7
7.7.8
Accelerated Program
Unlock Bypass
Accelerated single word programming and write buffer programming operations are enabled through the
WP#/ACC pin. This method is faster than the standard program command sequences.
Note
The accelerated program functions must not be used more than 10 times per sector.
If the system asserts V
mode and uses the higher voltage on the input to reduce the time required for program operations. The
system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note
that if a “Write-to-Buffer-Abort Reset” is required while in Unlock Bypass mode, the full 3-cycle RESET
command sequence must be used to reset the device. Removing V
of the embedded program operation, returns the device to normal operation.
 Sectors must be unlocked prior to raising WP#/ACC to V
 The WP#/ACC pin must not be at V
 It is recommended that WP#/ACC apply V
This device features an Unlock Bypass mode to facilitate shorter programming commands. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal
four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. The Command Definitions
the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Program, Write Buffer Programming, Write-to-Buffer-Abort
Reset, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. The first cycle address is “don't care” and the data 90h. The second cycle need only contain the
data 00h. The sector then returns to the read mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions.
Refer to the Spansion Low Level Driver User’s Guide (available soon on www.spansion.com) for general
information on Spansion Flash memory software development guidelines.
Cycle
damage may result.
recommended that WP#/ACC apply from V
/* Example: Unlock Bypass Entry Command
1
2
3
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0020;
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
Entry Command
Description
Unlock
Unlock
HH
D a t a
on this input, the device automatically enters the aforementioned Unlock Bypass
S29GL-P MirrorBit
(LLD Function = lld_UnlockBypassEntryCmd)
S h e e t
Table 7.14 Unlock Bypass Entry
Operation
HH
Write
Write
Write
for operations other than accelerated programming, or device
HH
HH
®
after power-up sequence is completed. In addition, it is
*/
Flash Family
to V
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
IH
Byte Address
Base + AAAh
Base + AAAh
Base + 555h
/V
IL
HH
before powering down V
.
HH
on page 68
*/
*/
*/
*/
*/
from the ACC input, upon completion
Word Address
Base + 2AAh
Base + 555h
Base + 555h
shows the requirements for
CC
/V
IO
*/
*/
*/
.
00AAh
0020h
0055h
Data
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