ISL6561CRZ Intersil, ISL6561CRZ Datasheet - Page 10

• Manufacturer Part Number: ISL6561CRZ
• Description: IC CTRLR PWM MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6561CRZ

• Applications: Controller, Intel VR10X
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 4
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Input Voltage: 12V
• Output Voltage: 1.65V
• Supply Voltage Range: 4.75V To 5.25V
• Digital Ic Case Style: QFN
• No. Of Pins: 40
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Control Mode: Voltage
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Pin Description
VCC - Supplies all the power necessary to operate the chip.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply or through a series
300Ω resistor to a +12V supply.
GND - Bias and reference ground for the IC.
EN - This pin is a threshold-sensitive enable input for the
controller. Connecting the 12V supply to EN through an
appropriate resistor divider provides a means to synchronize
power-up of the controller and the MOSFET driver ICs.
When EN is driven above 1.24V, the ISL6561 is active
depending on status of ENLL, the internal POR, and pending
fault states. Driving EN below 1.14V will clear all fault states
and prime the ISL6556 to soft start when re-enabled.
ENLL - This pin is implemented in QFN ISL6561 only. It’s a
logic-level enable input for the controller. When asserted to a
logic high, the ISL6561 is active depending on status of EN,
the internal POR, VID inputs and pending fault states.
Deasserting ENLL will clear all fault states and prime the
ISL6561 to soft start when re-enabled.
FS - A resistor, placed from FS to ground will set the switch-
ing frequency. There is an inverse relationship between the
value of the resistor and the switching frequency. See Figure
15 and Equation 29.
VID4, VID3, VID2, VID1, VID0, and VID12.5 - These are the
inputs to the internal DAC that provides the reference voltage
for output regulation. Connect these pins either to open-drain
outputs with or without external pull-up resistors or to active-
pull-up outputs. VID4-VID12.5 have 50uA internal pull-up
current sources that diminish to zero as the voltage rises
above the logic-high level. These inputs can be pulled up as
high as VCC plus 0.3V.
VDIFF, VSEN, and RGND - VSEN and RGND form the
precision differential remote-sense amplifier. This amplifier
converts the differential voltage of the remote output to a
single-ended voltage referenced to local ground. VDIFF is
the amplifier’s output and the input to the regulation and
protection circuitry. Connect VSEN and RGND to the sense
pins of the remote load.
FB and COMP - Inverting input and output of the error
amplifier respectively. FB is connected to VDIFF through a
resistor. A negative current, proportional to output current is
present on the FB pin. A properly sized resistor between
VDIFF and FB sets the load line (droop). The droop scale
factor is set by the ratio of the ISEN resistors and the lower
MOSFET r
external R-C network to compensate the regulator.
DAC and REF - The DAC output pin is the output of the
precision internal DAC reference. The REF input pin is the
positive input of the Error Amp. In typical applications, a 1kΩ,
DS(ON)
. COMP is tied back to FB through an
10
ISL6561
1% resistor is used between DAC and REF to generate a
precise offset voltage. This voltage is proportional to the
offset current determined by the offset resistor from OFS to
ground or VCC. A capacitor is used between REF and
ground to smooth the voltage transition during Dynamic
VID™ operations.
PWM1, PWM2, PWM3, PWM4 - Pulse-width modulation
outputs. Connect these pins to the PWM input pins of the
Intersil driver IC. The number of active channels is
determined by the state of PWM3 and PWM4. Tie PWM3 to
VCC to configure for 2-phase operation. Tie PWM4 to VCC
to configure for 3-phase operation.
ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;
ISEN4+, ISEN4- - The ISEN+ and ISEN- pins are current
sense inputs to individual differential amplifiers.he sensed
current is used as a reference for channel balancing,
protection, and regulation. Inactive channels should have
their respective current sense inputs left open (for example,
for 3-phase operation open ISEN4+).
For DCR sensing, connect each ISEN- pin to the node
between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, R
The voltage across the sense capacitor is proportional to the
inductor current. The sense current is proportional to the
output current, and scaled by the DCR of the inductor,
divided by R
When configured for r
ISEN2-, ISEN3-, and ISEN4- pins are grounded at the lower
MOSFET sources. The ISEN1+, ISEN2+, ISEN3+, and
ISEN4+ pins are then held at a virtual ground, such that a
resistor connected between them, and the drain terminal of
the associated lower MOSET, will carry a current
proportional to the current flowing through that channel. The
current is determined by the negative voltage developed
across the lower MOSFET’s r
current scaled by r
PGOOD - PGOOD is used as an indication of the end of
soft-start per Intel VR10. It is an open-drain logic output that
is low impedance until the soft start is completed. It will be
pulled low again once the under-voltage point is reached.
OFS - The OFS pin provides a means to program a dc offset
current for generating a dc offset voltage at the REF input.
The offset current is generated via an external resistor and
precision internal voltage references. The polarity of the
offset is selected by connecting the resistor to GND or VCC.
For no offset, the OFS pin should be left unterminated.
TCOMP - Temperature compensation scaling input. A
resistor from this pin to ground scales temperature
compensation of internal thermal sense circuitry. The
sensed temperature is utilized to modify the droop current
output to FB to adjust for MOSFET r
variations with temperature.
ISEN
.
DS(ON)
DS(ON)
.
DS(ON)
current sensing, the ISEN1-,
DS(ON)
, which is the channel
or inductor DCR
May 12, 2005
ISEN
FN9098.5
.