ISL6561CRZ Intersil, ISL6561CRZ Datasheet - Page 21

• Manufacturer Part Number: ISL6561CRZ
• Description: IC CTRLR PWM MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6561CRZ

• Applications: Controller, Intel VR10X
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 4
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Input Voltage: 12V
• Output Voltage: 1.65V
• Supply Voltage Range: 4.75V To 5.25V
• Digital Ic Case Style: QFN
• No. Of Pins: 40
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Control Mode: Voltage
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In Equation 22, make sure that ∆T
rise above the ambient temperature, and ∆T
temperature rise above the ambient temperature. While a
single adjustment according to Equation 22 is usually
sufficient, it may occasionally be necessary to adjust R
two or more times to achieve optimal thermal balance
between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R
Its value depends on the desired full-load droop voltage
(V
ISEN resistor, the load-line regulation resistor is as shown
in Equation 23.
If one or more of the ISEN resistors is adjusted for thermal
balance, as in Equation 23, the load-line regulation resistor
should be selected according to Equation 24 where I
full-load operating current and R
connected to the n
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
Since the system poles and zero are effected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
R
R
FB
FB
DROOP
=
=
V
------------------------ -
--------------------------------
I
70 10
FL
V
DROOP
DROOP
in Figure 7). If Equation 21 is used to select each
×
r
DS ON
–
(
6
)
th
∑
n
ISEN pin.
R
ISEN n ( )
21
C
and C
ISEN(n)
2
is the desired temperature
C
.
is the ISEN resistor
1
is the measured
FB
in Figure 7.
FL
(EQ. 24)
(EQ. 23)
ISEN
is the
ISL6561
The feedback resistor, R
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
In Equations 25, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and V
the peak-to-peak sawtooth signal amplitude as described in
Figure 6 and Electrical Specifications.
Case 2:
Case 3:
Case 1:
FIGURE 13. COMPENSATION CONFIGURATION FOR
R
FB
LOAD-LINE REGULATED ISL6561 CIRCUIT
R
C
-------------------
2π LC
V
f
R
C
+
C
C
-
0
DROOP
R
C
-------------------
2π LC
R
1
C
C
>
C
C
=
=
C
1
=
=
----------------------------- -
2πC ESR
R
=
=
------------------------------------------------------------ -
(
C
2π
≤
R
0.75V
------------------------------------------------ -
2
FB
FB
R
----------------------------------- -
2πV
2πV
C
(OPTIONAL)
f
FB
)
(
>
0
FB
1
C
V
--------------------------------------------
2
, has already been chosen as
0.75V
<
f
PP
0
f
----------------------------------------- -
0.75 V
PP
PP
2πf
----------------------------------- -
0
----------------------------- -
2πC ESR
0.75V
IN
2
0.75 V
(
V
2π f
0.75V
R
)
R
IDROOP
2π
(
0
PP
ESR
IN
FB
FB
COMP
VDIFF
V
(
1
)
0
IN
pp
IN
2
R
f
V
f
FB
0
IN
0
f
FB
(
IN
0
pp
) C
2
ESR
LC
)
L
LC
L
LC
0
)
. The target
May 12, 2005
(EQ. 25)
PP
FN9098.5
is
0