ISL6561CRZ Intersil, ISL6561CRZ Datasheet - Page 22

• Manufacturer Part Number: ISL6561CRZ
• Description: IC CTRLR PWM MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6561CRZ

• Applications: Controller, Intel VR10X
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 4
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Input Voltage: 12V
• Output Voltage: 1.65V
• Supply Voltage Range: 4.75V To 5.25V
• Digital Ic Case Style: QFN
• No. Of Pins: 40
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Control Mode: Voltage
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The optional capacitor C
noise away from the PWM comparator (see Figure 13). Keep
a position available for C
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
nce selected, the compensation values in Equations 23
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
value of R
oscilloscope until no further improvement is noted. Normally,
C
Equations 23 unless some performance issue is noted.
The optional capacitor C
noise away from the PWM comparator (see Figure 12). Keep
a position available for C
frequency capacitor of between 22pF and 150pF in case any
trailing edge jitter problem is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A type
III controller, as shown in Figure 14, provides the necessary
compensation.
The first step is to choose the desired bandwidth, f
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, f
noise rejection or to assure adequate attenuation at the error-
amplifier high-order pole and zero frequencies. A good general
rule is to chose f
Choosing f
too much phase shift below the system bandwidth.
In the solutions to the compensation equations, there is a single
degree of freedom. For the solutions presented in Equations
C
FIGURE 14. COMPENSATION CIRCUIT FOR ISL6561 BASED
will not need adjustment. Keep the value of C
C
R
1
1
C
HF
while observing the transient performance on an
CONVERTER WITHOUT LOAD-LINE
REGULATION
to be lower than 10f
HF
R
= 10f
FB
R
C
C
0
2
2
2
2
, but it can be higher if desired.
2
, is sometimes needed to bypass
, is sometimes needed to bypass
, and be prepared to install a high-
, and be prepared to install a high-
HF
C
C
. This pole can be used for added
22
IDROOP
0
COMP
VDIFF
can cause problems with
FB
C
. Slowly increase the
0
C
, of the
from
ISL6561
26, R
components are then selected according to Equations 26.
R
C
C
R
C
In Equations 26, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and V
the peak-to-peak sawtooth signal amplitude as described in
Figure 6 and Electrical Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy until the regulator can respond.
Because it has a low bandwidth compared to the switching
frequency, the output filter necessarily limits the system
transient response. The output capacitor must supply or sink
load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ∆V
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
1
1
2
C
C
=
=
=
=
=
FB
R
---------------------------------------- -
------------------------------------------------------------------ -
(
-------------------------------------------------------------------- -
0.75 V
------------------------------------------------------------------ -
(
2π
0.75V
2π
V
LC C ESR
FB
is selected arbitrarily. The remaining compensation
PP
)
)
2
---------------------------------------- -
2
–
R
f


f
MAX
LC C ESR
0
IN
2π
0
FB
IN
f
C ESR
f
0.75V
HF
(
HF




–
(


2πf
2πf
2
. Capacitors are characterized according to
f
0
LCR
(
LCR
HF
f
HF
IN
)
HF
)
LCR
FB
LC 1
FB
LC 1
)
V
V
–
–
PP
FB
PP




May 12, 2005
(EQ. 26)
PP
FN9098.5
is