ISL6561CRZ Intersil, ISL6561CRZ Datasheet - Page 17

• Manufacturer Part Number: ISL6561CRZ
• Description: IC CTRLR PWM MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6561CRZ

• Applications: Controller, Intel VR10X
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 4
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Input Voltage: 12V
• Output Voltage: 1.65V
• Supply Voltage Range: 4.75V To 5.25V
• Digital Ic Case Style: QFN
• No. Of Pins: 40
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Control Mode: Voltage
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

tracks the lower MOSFET or inductor temperature. The
value of K
temperature dependant transconductance of internal
compensation circuit. Its vaule is designed as 1µA/V/°C. The
temperature coefficient of MOSFET r
DCR is given by
resistance and the change in temperature. Resistance is
normalized to the value at 25°C and the value of
typically between 0.35%/°C and 0.50%/°C. For copper
wound inductors,
According to Equation 13, a voltage regulator with 80%
thermal coupling coefficient between the controller and lower
MOSFET and 0.4%/°C temperature coefficient of MOSFET
r
Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, PGOOD asserts
logic 1.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6561 is
released from shutdown mode.
DS(ON)
FIGURE 9. POWER SEQUENCING USING THRESHOLD-
FAULT LOGIC
CIRCUIT
SOFT START
requires a 5kΩ TCOMP resistor.
POR
T
AND
ISL6561 INTERNAL CIRCUIT
is typically between 75% and100%. K
SENSITIVE ENABLE (EN) FUNCTION
α
α
. This is the ratio of the change in
is 0.39%/°C.
ENABLE
COMPARATOR
17
+
-
1.24V
DS(ON)
EXTERNAL CIRCUIT
VCC
EN
ENLL
10.7kΩ
1.40kΩ
or Inductor
+12V
α
TC
is
is the
ISL6561
1 - The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this threshold
is reached, proper operation of all aspects of the ISL6561 is
guaranteed. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6561 will not
inadvertently turn off unless the bias voltage drops
substantially (see Electrical Specifications).
2 - The ISL6561 features an enable input (EN) for power
sequencing between the controller bias voltage and another
voltage rail. The enable comparator holds the ISL6561 in
shutdown until the voltage at EN rises above 1.24V. The
enable comparator has about 100mV of hysteresis to
prevent bounce. It is important that the driver ICs reach their
POR level before the ISL6561 becomes enabled. The
schematic in Figure 9 demonstrates sequencing the ISL6561
with the HIP660X family of Intersil MOSFET drivers, which
require 12V bias.
3 - The voltage on ENLL must be logic high to enable the
controller. This pin is typically connected to the
VID_PGOOD.
4 - The VID code must not be 111111 or 111110. These
codes signal the controller that no load is present. The
controller will enter shut-down mode after receiving either of
these codes and will execute soft start upon receiving any
other code. These codes can be used to enable or disable
the controller but it is not recommended. After receiving one
of these codes, the controller executes a 2-cycle delay
before changing the overvoltage trip level to the shut-down
level and disabling PWM. Overvoltage shutdown cannot be
reset using one of these codes.
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.24V; for
ISL6561CR, ENLL must be logic high; and VID cannot be
equal to 111111 or 111110. When each of these conditions
is true, the controller immediately begins the soft-start
sequence.
Soft-Start
During soft start, the DAC voltage ramps linearly from zero to
the programmed VID level as shown in Figure 10. The PWM
signals remain in the high-impedance state until the
controller detects that the ramping DAC level has reached
the output-voltage level. This protects the system against the
large, negative inductor currents that would otherwise occur
when starting with a pre-existing charge on the output as the
controller attempted to regulate to zero volts at the beginning
of the soft-start cycle. The soft-start time, t
delay period equal to 64 switching cycles followed by a linear
ramp with a rate determined by the switching period, 1/f
t
SS
=
64
-----------------------------------------
+
1280 VID
f
SW
⋅
SS
, begins with a
May 12, 2005
(EQ. 14)
FN9098.5
SW
.