IDT72V36102L10PF IDT, Integrated Device Technology Inc, IDT72V36102L10PF Datasheet

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IDT72V36102L10PF

Manufacturer Part Number
IDT72V36102L10PF
Description
IC FIFO 262KX18 10NS 120QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V36102L10PF

Function
Synchronous
Memory Size
4.7Mb (262k x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP, 120-VQFP
Configuration
Dual
Density
4.5Mb
Access Time (max)
6.5ns
Word Size
36b
Organization
64Kx36x2
Sync/async
Synchronous
Expandable
No
Bus Direction
Bi-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
400mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V36102L10PF

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V36102L10PF
Manufacturer:
TI
Quantity:
1 400
Part Number:
IDT72V36102L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V36102L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V36102L10PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V36102L10PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
©
FEATURES
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
Memory storage capacity:
Supports clock frequencies up to 100MHz
Fast access times of 6.5ns
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Two independent clocked FIFOs buffering data in opposite direc-
tions
2009
IDT72V3682 – 16,384 x 36 x 2
IDT72V3692 – 32,768 x 36 x 2
IDT72V36102 – 65,536 x 36 x 2
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
EFA/ORA
FFA/IRA
A
MBF2
CLKA
0
W/RA
RST1
MBA
CSA
ENA
- A
AEA
AFA
FS
FS
35
0
1
Control
Port-A
FIFO1,
Mail1
Reset
Logic
Logic
36
36
16
Programmable Flag
FIFO 1
Offset Registers
FIFO 2
Pointer
Pointer
Write
Read
3.3 VOLT CMOS SyncBiFIFO
16,384 x 36 x 2
32,768 x 36 x 2
65,536 x 36 x 2
16,384 x 36
32,768 x 36
65,536 x 36
16,384 x 36
32,768 x 36
65,536 x 36
Status Flag
Status Flag
Register
ARRAY
ARRAY
Register
Mail 1
Mail 2
Logic
Logic
RAM
RAM
1
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
Timing
Mode
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
Available in space-saving 120-pin Thin Quad Flatpack (TQFP)
Pin compatible to the lower density parts, IDT72V3622/72V3632/
72V3642/72V3652/72V3662/72V3672
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
Pointer
Pointer
Read
Write
TM
36
36
Control
FIFO2,
Mail2
Reset
Logic
Port-B
Logic
FEBRUARY 2009
4679 drw 01
IDT72V36102
EFB/ORB
FWFT
AEB
B
FFB/IRB
AFB
MBF1
IDT72V3682
IDT72V3692
0
RST2
CLKB
CSB
W/RB
ENB
MBB
- B
35
DSC-4679/6

Related parts for IDT72V36102L10PF

IDT72V36102L10PF Summary of contents

Page 1

FEATURES • • • • • Memory storage capacity: IDT72V3682 – 16,384 IDT72V3692 – 32,768 IDT72V36102 – 65,536 • • • • • Supports clock frequencies up to ...

Page 2

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 DESCRIPTION The IDT72V3682/72V3692/72V36102 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are mono- lithic, ...

Page 3

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB). The EF and FF functions are selected in the IDT ...

Page 4

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/0 AEA Port A Almost- O Empty Flag (Port A) less ...

Page 5

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O MBA Port A Mailbox I Select MBB Port B Mailbox I Select MBF1 Mail1 ...

Page 6

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC V (2) Input ...

Page 7

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously ...

Page 8

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE ο ο (Vcc = 3.3V 0.15V T = ...

Page 9

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C ο ο (Vcc = 3.3V 0.15V T ...

Page 10

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 SIGNAL DESCRIPTION RESET After power up, a Master Reset operation must be performed by providing a LOW pulse to RST1 ...

Page 11

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values ...

Page 12

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done ...

Page 13

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the ...

Page 14

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKA CLKB t RSTS RST1 FWFT FS1,FS0 FFA/IRA EFB/ORB t PRF AEB t PRF AFA t PRF MBF1 NOTES: 1. ...

Page 15

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t CLKH t CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ...

Page 16

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t CLKH CLKB EFB/ORB HIGH CSB W/RB MBB ENB t EN B0-B35 (IDT Standard Mode ...

Page 17

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKA CSA LOW HIGH WRA t t ENS2 ENH MBA t ENS2 t ENH ENA HIGH IRA ...

Page 18

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKA CSA LOW WRA HIGH t t ENS2 MBA t t ENS2 ENA FFA HIGH t DS A0-A35 W1 t ...

Page 19

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH ...

Page 20

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKB CSB LOW W/RB LOW t t ENS2 MBB t t ENS2 ENB FFB HIGH B0-B35 ...

Page 21

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB HIGH ORB B0 -B35 ...

Page 22

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB EFB HIGH B0-B35 Previous ...

Page 23

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t t CLKH CLKL CLKA CSA LOW W/RA LOW MBA LOW t ENS2 ENA HIGH ORA A0 -A35 ...

Page 24

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH A0-A35 Previous ...

Page 25

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKB t t ENS2 ENH ENB t SKEW2 CLKA AEA X2 Words in FIFO2 ENA NOTES: is the minimum time ...

Page 26

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKB t t ENS2 ENB AFB [D-(Y2+1)] Words in FIFO2 CLKA ENA NOTES: is the minimum time between a rising ...

Page 27

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKB t ENS1 CSB t ENS1 W/RB t ENS2 MBB t ENS2 ENB B0 - B35 CLKA MBF2 CSA W/RA ...

Page 28

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 Timing Input t S Data, 1.5V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5V t PLZ Low-Level ...

Page 29

ORDERING INFORMATION XXXXXX Device Type Power Speed Package NOTES: 1. Industrial temperature range is available by special order. 2. Green parts available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 10/30/2000 pgs. 1, ...

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