DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 142

IC DSPIC MCU/DSP 6K 28SOIC

DSPIC30F1010-30I/SO

Manufacturer Part Number
DSPIC30F1010-30I/SO
Description
IC DSPIC MCU/DSP 6K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit
Number Of Timers
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
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Manufacturer
Quantity
Price
Part Number:
DSPIC30F1010-30I/SO
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Microchip Technology
Quantity:
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dsPIC30F1010/202X
12.35 METHODS TO REDUCE EMI
The goal is to move the PWM edges around in time to
spread the EMI energy over a range of frequencies to
reduce the peak energy at any given frequency during
the EMI measurement process, which measures long
term averages.
The EMI measurement process integrates the EMI
energy into 9 kHz wide frequency bins. Assuming that
the carrier (PWM) frequency is 150 kHz, a 6% dither
will yield a 9 kHz wide dither.
12.35.1 METHOD #1: PROGRAMMABLE FRC
This method dithers all of the PWM outputs and the
system clock. The advantage of this method is that no
CPU resources are required. It is automatic once it is
setup. The user can periodically update these values
to simulate a more random frequency pattern.
12.35.2 METHOD #2: SOFTWARE CONTROLLED
This method uses software to dither individual PWM
channels by scaling the duty cycle and period. This
method consumes CPU resources:
Assume:
4 PWM channels updated @ 150 kHz rate:
600 kHz x (5 clocks (2 mul, 1 tblrdl, 1 mov))
12.35.3 METHOD #3: SOFTWARE SCALING OF
This method used software to scale just the time base
period. Assuming that the dither rate is relatively slow
(about 250 Hz), the application control loop should be
able to compensate for the changes in PWM period
and adjust the duty cycle accordingly.
DS70178C-page 140
= 3 MIPS additional work load
DITHER
DITHER
TIME BASE PERIOD
Preliminary
12.35.4 METHOD #4: FREQUENCY MODULATION
This method varies the frequency at which the PWM
cycle is varied (dithered). The frequency modulation
process is similar (mathematically speaking) to Phase
Modulation when analyzed over a small time window.
The PWM module has the capability to phase modu-
late the PWM signals via the phase offset registers.
Phase modulation has the advantage that the software
is simpler and faster because multiple multiply opera-
tions (used for dithering frequency by scaling period
and duty cycles) are replaced with fewer additions or
simple updates of phase offset
values into the phase registers.
This method also has these advantages:
1.
2.
This method has one disadvantage: the phase modu-
lation has to be at a relatively high update rate to
achieve usable frequency spreading.
12.35.5 INDEPENDENT PWM CHANNEL
Issues for multi-phase or variable phase designs using
independent output dithering must consider these
issues:
1.
2.
Multi-phase and variable phase PWM modes
could still be created.
The PWM generators can still use the common
time base, which simplifies determining when a
“quiet time” is available for measuring current.
The phases are no longer phase aligned.
Control of current sharing among phases is
more difficult.
DITHERING ISSUES:
© 2006 Microchip Technology Inc.

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