DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 216

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
18.8
18.8.1
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer, which
runs off an on-chip RC oscillator, requiring no external
component. Therefore, the WDT timer will continue to
operate even if the main processor clock (e.g., the
crystal oscillator) fails.
18.8.2
The Watchdog Timer can be “enabled” or “disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register FWDT.
Setting FWDTEN = 1 enables the Watchdog Timer.
The enabling is done when programming the device.
By default, after chip-erase, FWDTEN bit = 1. Any
device
dsPIC30F devices allows programming of this and
other Configuration bits.
If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device will wake-
up. The WDTO bit in the RCON register will be cleared
to indicate a wake-up resulting from a WDT time-out.
Setting FWDTEN = 0 allows user software to enable/
disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
18.9
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV.
These are: Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV <parameter>, where ‘parameter’ defines
Idle or Sleep mode.
18.9.1
In Sleep mode, the clock to the CPU and peripherals is
shutdown. If an on-chip oscillator is being used, it is
shutdown.
The Fail-Safe Clock Monitor is not functional during
Sleep, since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational during
Sleep.
DS70178C-page 214
Power-Saving Modes
programmer
Watchdog Timer (WDT)
WATCHDOG TIMER OPERATION
ENABLING AND DISABLING THE
WDT
SLEEP MODE
capable
of
programming
Preliminary
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
• any interrupt that is individually enabled and
• any Reset (POR and MCLR)
• WDT time-out
On waking up from Sleep mode, the processor will
restart the same clock that was active prior to entry
into Sleep mode. When clock switching is enabled,
bits COSC<2:0> will determine the oscillator source
that will be used on wake-up. If clock switch is
disabled, then there is only one system clock.
If the clock source is an oscillator, the clock to the
device is held off until OST times out (indicating a sta-
ble oscillator). If PLL is used, the system clock is held
off until LOCK = 1 (indicating that the PLL is stable).
Either way, T
If EC, FRC, oscillators are used, then a delay of T
(~10 s) is applied. This is the smallest delay possible
on wake-up from Sleep.
Moreover, if LP oscillator was active during Sleep, and
LP is the oscillator used on wake-up, then the start-up
delay will be equal to T
timer delay are not applied. In order to have the small-
est possible start-up delay when waking up from Sleep,
one of these faster wake-up options should be selected
before entering Sleep.
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The proces-
sor will process the interrupt and branch to the ISR. The
Sleep status bit in the RCON register is set upon
wake-up.
All Resets will wake-up the processor from Sleep
mode. Any Reset, other than POR, will set the Sleep
status bit. In a POR, the Sleep bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Sleep mode upon WDT time-out. The
Sleep and WDTO status bits are both set.
meets the required priority level
Note:
Note:
If a POR occurred, the selection of the
oscillator is based on the FOSC<2:0> and
FOSCSEL<1:0> Configuration bits.
In spite of various delays applied (T
T
(and PLL) may not be active at the end of
the time-out (e.g., for low frequency crys-
tals). In such cases, if FSCM is enabled, the
device will detect this as a clock failure and
process the clock failure trap, the FRC
oscillator will be enabled, and the user will
have to re-enable the crystal oscillator. If
FSCM is not enabled, then the device will
simply suspend execution of code until the
clock is stable, and will remain in Sleep until
the oscillator clock has started.
POR
LOCK
, T
LOCK
and T
and T
© 2006 Microchip Technology Inc.
POR
PWRT
. PWRT delay and OST
PWRT
), the crystal oscillator
delays are applied.
POR
POR
,