AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 124

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

12. Watchdog Timer (WDT)
12.1
12.2
12.3
Figure 12-1. Real Time Counter module block diagram
12.4
12.4.1
12.4.2
12.4.3
32054F–AVR32–09/09
Features
Description
Block Diagram
Product Dependencies
3 2 K H z
I/O Lines
Power Management
Debug Operation
1 6 -b it P r e s c a le r
Rev: 1.0.1
•
The Watchdog Timer (WDT) is fed from a 16-bit prescaler, which is clocked from the 32 kHz
oscillator. Any tapping of the prescaler can be selected as clock source for the WDT.The watch-
dog timer must be periodically reset by software within the timeout period, ot herwise, the device
is reset and starts executing from the boot vector. This allows the device to recover from a con-
dition that has caused the system to be unstable.
None
The WDT is continously clocked, and remains operating in all sleep modes. However, if the
WDT is enabled and the user tries to enter a sleepmode where the 32 KHz oscillator is turned off
the system will enter the STOP sleepmode instead. This is to ensure the WDT is still running.
The watchdog timer is frozen during debug operation, unless the OCD system keeps peripherals
running in debug operation.
Watchdog timer with 16-bit prescaler
W D T _ C T R L
W D T _ C L R
W a tc h d o g
D e te c to r
AT32AP7002
W a tc h d o g
r e s e t
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