AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 393

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 24-5. Elementary Time Unit (ETU)
24.7.2
24.7.3
24.7.3.1
32054F–AVR32–09/09
Receiver and Transmitter Control
Synchronous and Asynchronous Modes
Transmitter Operations
O7816 I/O Line
SO7816 Clock
on TXD
on CLK
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit
in the Control Register (CR). However, the receiver registers can be programmed before the
receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the
Control Register (CR). However, the transmitter registers can be programmed before being
enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by
setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (CR).
The reset commands have the same effect as a hardware reset on the corresponding logic.
Regardless of what the receiver or the transmitter is performing, the communication is immedi-
ately stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and
TXDIS respectively in CR. If the receiver is disabled during a character reception, the USART
waits until the end of reception of the current character, then the reception is stopped. If the
transmitter is disabled while it is operating, the USART waits the end of transmission of both the
current character and character being stored in the Transmit Holding Register (THR). If a time-
guard is programmed, it is handled normally.
The transmitter performs the same in both synchronous and asynchronous operating modes
(SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two
stop bits are successively shifted out on the TXD pin at each falling edge of the programmed
serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register
(MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity
bit is set according to the PAR field in MR. The even, odd, space, marked or none parity bit can
be configured. The MSBF field in MR configures which data bit is sent first. If written at 1, the
most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is
selected by the NBSTOP field in MR. The 1.5 stop bit is supported in asynchronous mode only.
ISO7816 Clock Cycles
FI_DI_RATIO
1 ETU
AT32AP7002
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