AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 759

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

34.7
34.8
32054F–AVR32–09/09
Interrupts
Configuration Sequence
The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal
LCDC Core Clock. The IRQs are:
Each IRQ can be individually enabled, disabled or cleared, in the IER (Interrupt Enable Regis-
ter), IDR (Interrupt Disable Register) and ICR (Interrupt Clear Register) registers. The IMR
register contains the mask value for each IRQ source and the LDC_ISR contains the status of
each IRQ source. A more detailed description of these registers can be found in
(LCDC) User Interface” on page
The DMA Controller starts to transfer image data when the LCDC Core is activated (Write to
PWR field of PWRCON register). Thus, the user should configure the LCDC Core and configure
and enable the DMA Controller prior to activation of the LCD Controller. In addition, the image
data to be shows should be available when the LCDC Core is activated, regardless of the value
programmed in the GUARD_TIME field of the PWRCON register.
To disable the LCD Controller, the user should disable the LCDC Core and then disable the
DMA Controller. The user should not enable the LCDC again until the LCDC Core is in IDLE
state. This is checked by reading the BUSY bit in the PWRCON register.
The initialization sequence that the user should follow to make the LCDC work is:
•DMA Memory error IRQ. Generated when the DMA receives an error response from an HSB
•FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when
•FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO
•DMA end of frame IRQ. Generated when the DMA controller updates the Frame Base
•End of Line IRQ. This IRQ is generated when the LINEBLANK period of each line is reached
•End of Last Line IRQ. This IRQ is generated when the LINEBLANK period of the last line of
•Create or copy the first image to show in the display buffer memory.
•If a palletized mode is used, create and store a palette in the internal LCD Palette
•Configure the LCD Controller Core without enabling it:
slave while it is doing a data transfer.
the FIFO is empty.
while the FIFO is full.
Address pointers. This IRQ can be used to implement a double-buffer technique. For more
information, see
and the DMA Controller is in inactive state.
the current frame is reached and the DMA Controller is in inactive state.
memory(See Section “34.6.2.5” on page 743.
– LCDCON1 register: Program the CLKVAL and BYPASS fields: these fields control the
pixel clock divisor that is used to generate the pixel clock PCLK. The value to program
depends on the LCDC Core Clock and on the type and size of the LCD Module used.
There is a minimum value of the PCLK clock period that depends on the LCD
Controller Configuration, this minimum value can be found in
748. The equations that are used to calculate the value of the pixel clock divisor can
be found at the end of the section
”Double-buffer Technique” on page
767.
”Timegen” on page 747
761.
Table 34-11 on page
AT32AP7002
”LCD Controller
759