AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 747

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Table 34-10. Dithering Algorithm for Color Mode (Continued)
Note:
34.6.2.7
34.6.2.8
32054F–AVR32–09/09
Frame
N+2
N+2
N+2
N+2
N+2
…
Ri = red pixel component ON. Gi = green pixel component ON. Bi = blue pixel component ON. ri = red pixel component OFF.
gi = green pixel component OFF. bi = blue pixel component OFF.
green_data_0
green_data_1
blue_data_0
blue_data_1
Shifter
Timegen
red_data_1
Signal
…
The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome
mode and three sub-pixels at a time in color mode (R,G,B components). This module packs the
data according to the output interface. This interface can be programmed in the DISTYPE,
SCANMOD, and IFWIDTH fields of the LCDCON2 register.
The DISTYPE field selects between TFT, STN monochrome and STN color display. The SCAN-
MODE field selects between single and dual scan modes; in TFT mode, only single scan is
supported. The IFWIDTH field configures the width of the interface in STN mode: 4-bit (in single
scan mode only), 8-bit and 16-bit (in dual scan mode only).
For a more detailed description of the fields, see
page
For a more detailed description of the LCD Interface, see
The time generator block generates the control signals PCLK, HSYNC, VSYNC, DVAL, and
MODE, used by the LCD module. This block is programmable in order to support different types
of LCD modules and obtain the output clock signals, which are derived from the LCDC Core
Clock.
The MODE signal provides an AC signal for the display. It is used by the LCD to alternate the
polarity of the row and column voltages used to turn the pixels on and off. This prevents the liq-
uid crystal from degradation. It can be configured to toggle every frame (bit MMODE = 0 in
LCDMVAL register) or to toggle every programmable number of HSYNC pulses (bit MMODE =
1, number of pulses defined in MVAL field of LCDMVAL register).
Figure 34-3
Shadow Level
767.
1010
1010
1010
1010
1010
…
and
f
LCD_MODE
Figure 34-4 on page 748
Bit used
…
0
2
1
3
2
=
--------------------------------------- -
2
f
×
LCD_HSYNC
(
MVAL
Dithering Pattern
+
0110
0110
0110
0110
0110
1
show the timing of MODE in both configurations.
…
)
”LCD Controller (LCDC) User Interface” on
4-bit LCDD
”LCD Interface” on page
LCDD[2]
LCDD[1]
LCDD[0]
LCDD[3]
LCDD[2]
…
AT32AP7002
8-bit LCDD
LCDD[6]
LCDD[5]
LCDD[4]
LCDD[3]
LCDD[2]
…
753.
Output
G0
B0
B1
g1
…
r1
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