AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 143

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

15.4.3.1
32054F–AVR32–09/09
Arbitration Rules
When a re-arbitration must be done, specific conditions apply. See
Rules” on page
Each arbiter has the ability to arbitrate between two or more different master requests. In order
to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra-
tion may only take place during the following cycles:
• Undefined Length Burst Arbitration
In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix pro-
vides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end
of burst is used as a defined length burst transfer and can be selected from among the following
five possibilities:
This selection can be done through the field ULBT of the Master Configuration Registers
(MCFG).
• Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a
very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a
counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave
Configuration Register (SCFG) and decreased at each clock cycle. When the counter reaches
zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word
transfer.
1. Idle Cycles: When a slave is not connected to any master or is connected to a master
2. Single Cycles: When a slave is currently doing a single access.
3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For
4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that
1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will
2. One beat bursts: Predicted end of burst is generated at each single transfer inside the
3. Four beat bursts: Predicted end of burst is generated at the end of each four beat bound-
4. Eight beat bursts: Predicted end of burst is generated at the end of each eight beat
5. Sixteen beat bursts: Predicted end of burst is generated at the end of each sixteen beat
which is not currently accessing it.
defined length burst, predicted end of burst matches the size of the transfer but is man-
aged differently for undefined length burst.
the current master access is too long and must be broken.
never be broken.
INCP transfer.
ary inside INCR transfer.
boundary inside INCR transfer.
boundary inside INCR transfer.
143.
See Section “•” on page 143.
See Section “•” on page 143.
Section 15.4.3.1 ”Arbitration
AT32AP7002
143