AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 249

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

19.5.1
19.5.2
19.5.3
19.5.4
32054F–AVR32–09/09
Pull-up Resistor Control
I/O Line or Peripheral Function Selection
Peripheral A or B Selection
Output Control
Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled
or disabled by writing respectively PUER (Pull-up Enable Register) and PUDR (Pull-up Disable
Resistor). Writing in these registers results in setting or clearing the corresponding bit in PUSR
(Pull-up Status Register). Reading a 1 in PUSR means the pull-up is disabled and reading a 0
means the pull-up is enabled.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PUSR resets at the value 0x0.
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with
the registers PER (PIO Enable Register) and PDR (PIO Disable Register). The register PSR
(PIO Status Register) is the result of the set and clear registers and indicates whether the pin is
controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that
the pin is controlled by the corresponding on-chip peripheral selected in the ABSR (AB Select
Status Register). A value of 1 indicates the pin is controlled by the PIO controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PER
and PDR have no effect and PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PSR resets at
1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in
the case of memory chip select lines that must be driven inactive after reset or for address lines
that must be driven low for booting out of an external memory). Thus, the reset value of PSR is
defined at the product level, depending on the multiplexing of the device.
The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The
selection is performed by writing ASR (A Select Register) and BSR (Select B Register). ABSR
(AB Select Status Register) indicates which peripheral line is currently selected. For each pin,
the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at
level 1 indicates that peripheral B is selected.
Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral
input lines are always connected to the pin input.
After reset, ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. How-
ever, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.
Writing in ASR and BSR manages ABSR regardless of the configuration of the pin. However,
assignment of a pin to a peripheral function requires a write in the corresponding peripheral
selection register (ASR or BSR) in addition to a write in PDR.
When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PSR is at 0,
the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value
in ABSR, determines whether the pin is driven or not.
When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This
is done by writing OER (Output Enable Register) and ODR (Output Disable Register). The
results of these write operations are detected in OSR (Output Status Register). When a bit in this
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