AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 464
AT32AP7002-CTUT
Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7002-CTUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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25.8.11
Register Name:
Access Type:
• DMAEN: DMA Enable
0: Disable DMA transfers for this channel.
1: Enable DMA transfers for this channel using DMAC.
• CEM: Channel A Endian Mode
0: Transferring Data through Channel A is straight forward (Big Endian).
1: Transferring Data through Channel A from/to a memory is performed with from/to Little Endian format translation.
• SIZE: Channel A Data Size
SIZE Encoding
Note:
• CEN: Channel A Enable
0: Data transfer is disabled on Channel A.
1: Data transfer is enabled on Channel A.
32054F–AVR32–09/09
31
23
15
–
–
–
7
–
Each time slot in the data phase is 20 bit long. For example, if a 16-bit sample stream is being played to an AC 97 DAC, the first
16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the AC97 Controller
fills with zeroes. This process ensures that the least significant bits do not introduce any DC biasing, regardless of the imple-
mented DAC’s resolution (16-, 18-, or 20-bit).
SIZE
AC97 Controller Channel A Mode Register
0x0
0x1
0x2
0x3
DMAEN
30
22
14
–
–
6
–
Selected Channel
20 bits
18bits
16 bits
10 bits
OVRUN
CEN
29
21
13
–
–
5
CAMR
Read/Write
RXRDY
28
20
12
–
–
–
4
27
19
11
–
–
–
3
–
UNRUN
CEM
26
18
10
–
–
2
TXEMPTY
AT32AP7002
25
17
–
9
–
1
SIZE
TXRDY
24
16
–
8
–
0
464
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