AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 516

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 27-34. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow
27.6.9
27.6.9.1
32054F–AVR32–09/09
Internal signal from PM
Slow Clock Mode
NBS0, NBS1,
Asynchronous Page Mode
A0, A1
CLK_SMC
Protocol and timings in page mode
A[25:2]
Clock Mode
NWE
NCS
The SMC supports asynchronous burst reads in page mode, providing that the Page Mode
Enabled bit is written to one in the MODE register (MODE.PMEN). The page size must be con-
figured in the Page Size field in the MODE register (MODE.PS) to 4, 8, 16, or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in
With page mode memory devices, the first access to one page (t
quent accesses to the page (t
the SMC enables the user to define different read timings for the first access within one page,
and next accesses within the page.
Table 27-5.
Notes:
Figure 27-35 on page 517
SLOW CLOCK MODE WRITE
Page Size
4 bytes
8 bytes
16 bytes
32 bytes
1
1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.
1
Page Address and Data Address within a Page
Page Address
A[25:2]
A[25:3]
A[25:4]
A[25:5]
1
shows the NRD and NCS timings in page mode access.
sa
) as shown in
(1)
IDLE STATE
Table 27-5 on page
Figure 27-35 on page
Reload Configuration
Data Address in the Page
A[1:0]
A[2:0]
A[3:0]
A[4:0]
Wait State
2
pa
NORMAL MODE WRITE
) takes longer than the subse-
516.
517. When in page mode,
AT32AP7002
3
(2)
2
516