AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 661

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

• ERR_OVFLW: Overflow Error
This bit is set by hardware when a new too-long packet is received.
Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Over-
flow Error bit is set.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by EPTRST register RST_EPT_x (reset endpoint) and by EPTCTLDISx (disable endpoint).
• RX_BK_RDY/KILL_BANK: Received OUT Data/KILL Bank
Received OUT Data: (For OUT endpoint or Control endpoint)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO.
This bit is cleared by the device firmware after reading the OUT data from the endpoint.
For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has
been received meanwhile.
Hardware assertion of this bit may generate an interrupt if enabled by the EPTCTLx register RX_BK_RDY bit.
This bit is reset by EPTRST register RST_EPT_x (reset endpoint) and by EPTCTLDISx (disable endpoint).
KILL Bank: (For IN endpoint)
Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the USBA
line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is
no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the
last bank is killed.
• TX_COMPLT: Transmitted IN Data Complete
This bit is set by hardware after an IN packet has been transmitted for isochronous endpoints and after it has been
accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints.
This bit is reset by EPTRST register RST_EPT_x (reset endpoint), and by EPTCTLDISx (disable endpoint).
• TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error
TX Packet Ready:
This bit is cleared by hardware, as soon as the packet has been sent for isochronous endpoints, or after the host has
acknowledged the packet for Control, Bulk and Interrupt endpoints.
For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit.
Hardware clear of this bit may generate an interrupt if enabled by the EPTCTLx register TX_PK_RDY bit.
This bit is reset by EPTRST register RST_EPT_x (reset endpoint), and by EPTCTLDISx (disable endpoint).
Transaction Error: (For high bandwidth isochronous OUT endpoints) (Read-Only)
This bit is set by hardware when a transaction error occurs inside one microframe.
If one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe, then this bit is still
set as long as the current bank contains one “bad” n-transaction. (see
32054F–AVR32–09/09
– the bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented.
– the bank is not cleared but sent on the IN transfer, TX_COMPLT
– the bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear
another packet.
”CURRENT_BANK/CONTROL_DIR: Current
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