AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 449

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

25.7.3.6
25.7.3.7
25.7.3.8
25.7.3.9
32054F–AVR32–09/09
31
31
31
31
Byte3[7:0]
Configuring and Using Interrupts
Endianness
To Transmit a Word Stored in Little Endian Format on AC-link
To Transmit A Halfword Stored in Little Endian Format on AC-link
–
–
–
Instead of polling flags in AC97 Controller Global Status Register (SR) and in AC97 Controller
Channel x Status Register (CxSR), the application can wait for an interrupt notice. The following
steps show how to configure and use interrupts correctly:
The interrupt handler must read both AC97 Controller Global Status Register (SR) and AC97
Controller Interrupt Mask Register (IMR) and AND them to get the real interrupt source. Further-
more, to get which event was activated, the interrupt handler has to read AC97 Controller
Channel x Status Register (CxSR), x being the channel whose event triggers the interrupt.
The application can disable event interrupts by writing in AC97 Controller Interrupt Disable Reg-
ister (IDR). The AC97 Controller Interrupt Mask Register (IMR) shows which event can trigger
an interrupt and which one cannot.
Endianness can be managed automatically for each channel, except for the Codec channel, by
writing to Channel Endianness Mode (CEM) in CxMR. This enables transferring data on AC-link
in Little Endian format without any additional operation.
Word to be written in AC97 Controller Channel x Transmit Holding Register (CxTHR) (as it is
stored in memory or microprocessor register).
Word stored in Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit)
Data transmitted on appropriate slot: data[19:0] = {Byte1[3:0], Byte2[7:0], Byte3[7:0]}.
Halfword to be written in AC97 Controller Channel x Transmit Holding Register (CxTHR).
Halfword stored in AC97 Controller Channel x Transmit Holding Register (CxTHR) (data to
transmit).
Data emitted on related slot: data[19:0] = {Byte1[7:0], Byte0[7:0], 0x0}.
24
24
24
24
•Set the interruptible flag in AC97 Controller Channel x Mode Register (CxMR).
•Set the interruptible event and channel event in AC97 Controller Interrupt Enable Register
(IER).
23
23
23
23
–
Byte2[7:0]
20
–
–
19
Byte1[3:0]
16
16
16
16
15
15
15
15
Byte2[7:0]
Byte1[7:0]
Byte1[7:0]
Byte0[7:0]
8
8
8
8
7
7
7
7
AT32AP7002
Byte0[7:0]
Byte3[7:0]
Byte1[7:0]
Byte0[7:0]
.
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0
0
0
0