AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 556
AT32AP7002-CTUT
Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7002-CTUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 29-2. Parity Generation for 512/1024/2048/4096 8-bit Words1
32054F–AVR32–09/09
(page size -1 )th byte
(page size -2 )th byte
(page size -3 )th byte
Page size th byte
Page size = 512 Px = 2048
Page size = 1024 Px = 4096
Page size = 2048 Px = 8192
Page size = 4096 Px = 16384
4 th byte
2nd byte
3rd byte
1st byte
words. Of the 32 ECC bits, 26 bits are for line parity and 6 bits are for column parity. They are
generated according to the schemes shown in
To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
Bit7
Bit7
Bit7
Bit7
Bit7
Bit7
Bit7
Bit7
P1
P2
Page size = 2
Bit6
Bit6
Bit6
Bit6
Bit6
Bit6
Bit6
Bit6
for i =0 to n
begin
end
P1'
for (j = 0 to page_size_byte)
begin
if(j[i] ==1)
else
end
P4
P[2
P[2
Bit5
Bit5
Bit5
Bit5
Bit5
Bit5
Bit5
Bit5
P1
i+3
i+3
P2'
]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
]’=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
Bit4
Bit4
Bit4
Bit4
Bit4
Bit4
Bit4
Bit4
n
P1'
bit2(+)bit1(+)bit0(+)P[2
bit2(+)bit1(+)bit0(+)P[2
Bit3
Bit3
Bit3
Bit3
Bit3
Bit3
Bit3
Bit3
P1
P2
P1=bit7(+)bit5(+)bit3(+)bit1(+)P1
P2=bit7(+)bit6(+)bit3(+)bit2(+)P2
P4=bit7(+)bit6(+)bit5(+)bit4(+)P4
P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1'
P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2'
P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'
Bit2
Bit2
Bit2
Bit2
Bit2
Bit2
Bit2
Bit2
P1'
P4'
Bit1
Bit1
Bit1
Bit1
Bit1
Bit1
Bit1
Bit1
P1
P2'
Bit0
Bit0
Bit0
Bit0
Bit0
Bit0
Bit0
Bit0
Figure 29-2
P1'
i+3
P8
P8'
P8
P8'
P8
P8'
P8
P8'
i+3
]
]'
and
P16'
P16'
P16
P16
Figure
P32
P32
P32
29-3.
AT32AP7002
PX
PX'
556
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