DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 1047

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

All-module-clocks-stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ7 pins), RES
pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal
program execution state via the exception handling state. All-module-clocks-stop mode is not
cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the
relevant interrupt is designated as a DTC activation source.
When the STBY pin is driven low, a transition is made to hardware standby mode.
24.3
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 24.3 shows the state of the φ pin in each processing state.
Table 24.3 φ Pin State in Each Processing State
Register Setting
DDR
0
1
1
24.4
24.4.1
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current
dissipation for the output current when a high-level signal is output.
24.4.2
Current dissipation increases during the oscillation stabilization standby period.
PSTOP
X
0
1
φ Clock Output Control
Usage Notes
I/O Port Status
Current Dissipation during Oscillation Stabilization Standby Period
Normal operating
state
High impedance
φ output
Fixed high
Sleep mode
High impedance High impedance
φ output
Fixed high
Software
standby mode
Fixed high
Fixed high
Rev.7.00 Mar. 18, 2009 page 979 of 1136
Section 24 Power-Down Modes
Hardware
standby mode
High impedance
High impedance
High impedance
REJ09B0109-0700
All-module-
clocks-stop
mode
High impedance
φ output
Fixed high