DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 415

IC H8S/2378 MCU FLASH 144-QFP

DF2378BVFQ35WV

Manufacturer Part Number
DF2378BVFQ35WV
Description
IC H8S/2378 MCU FLASH 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2378BVFQ35WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
For Use With
EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2378BVFQ35WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 7.33 shows an example of single address transfer using the write data buffer function. In
this example, the CPU program area is in on-chip memory.
When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one
state after the start of the DMA write cycle or single address transfer.
7.5.12
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
7.11 summarizes the priority order for DMAC channels.
Table 7.11 DMAC Channel Priority Order
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function
Internal read signal
External address
Internal address
Multi-Channel Operation
DACK
RD
φ
DMA
read
DMA
single
Full Address Mode
Channel 0
Channel 1
CPU
read
Rev.7.00 Mar. 18, 2009 page 347 of 1136
Section 7 DMA Controller (DMAC)
DMA
single
Priority
High
Low
CPU
read
REJ09B0109-0700

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