DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 866

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
Rev.7.00 Mar. 18, 2009 page 798 of 1136
REJ09B0109-0700
Note: * Ensure that no interrupts are received while steps [1] through [3] are being processed.
Additional information: If only one byte is received, steps [2] through [6] are omitted following step [1],
No
No
No
Set ACKBT = 0 (ICIER)
Set ACKBT = 1 (ICIER)
Set RCVD = 0 (ICCRA)
Set RCVD - 1 (ICCRA)
Clear ACKBT in ICIER
Set MST = 0 (ICCRA)
Set TRS = 0 (ICCRA)
Clear TEND in ICSR
Clear TDRE of ICSR
Dummy read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Clear STOP of ICSR
Read STOP of ICSR
Mater receive mode
2
C Bus Interface 2 (IIC2) (Option)
Write BBSY = 0
Read ICDRR
Read ICDRR
Read ICDRR
(Last receive
and SCP = 0
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
- 1)?
End
Figure 16.15 Sample Flowchart for Master Receive Mode
Yes
Yes
Yes
No
and processing jumps to step [7].
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear STOP flag.
[11] Stop condition issuance.
[12] Wait for the creation of stop condition.
[13] Read the receive data of the final byte, and clear RDRF to 0.
[14] Clear RCVD to 0.
[15] Clear ACKBT.
[16] Set slave receive mode.
Clear TEND, select master receive mode, and then clear TDRE. *
Set acknowledge to the transmitting device. *
Dummy read ICDDR. *
Wait for 1 byte to be received.
Check if (last receive - 1).
Read the receive data, and clear RDRF to 0.
Set acknowledge of the final byte. Disable continuous receive (RCVD = 1).
Read receive data of (final byte - 1), and clear RDRF to 0.
Wait for the final byte to be received.