DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 46

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 3.9
Figure 3.10 Memory Map for H8S/2372 and H8S/2372R (1) ...................................................... 87
Figure 3.11 Memory Map for H8S/2372 and H8S/2372R (2) ...................................................... 88
Figure 3.12 Memory Map for H8S/2371 and H8S/2371R (1) ...................................................... 89
Figure 3.13 Memory Map for H8S/2371 and H8S/2371R (2) ...................................................... 90
Figure 3.14 Memory Map for H8S/2370 and H8S/2370R (1) ...................................................... 91
Figure 3.15 Memory Map for H8S/2370 and H8S/2370R (2) ...................................................... 92
Section 4 Exception Handling ............................................................................. 93
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Section 5 Interrupt Controller............................................................................ 103
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Section 6 Bus Controller (BSC) ........................................................................ 137
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space ........................................................... 179
Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space ........................................................... 180
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)........... 181
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) ............ 182
Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ................................ 183
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)........... 184
Rev.7.00 Mar. 18, 2009 page xliv of lxvi
REJ09B0109-0700
Memory Map for H8S/2373 and H8S/2373R............................................................ 86
Reset Sequence (Advanced Mode with On-chip ROM Enabled).............................. 96
Reset Sequence (Advanced Mode with On-chip ROM Disabled) ............................ 97
Stack Status after Exception Handling .................................................................... 100
Operation when SP Value Is Odd............................................................................ 101
Block Diagram of Interrupt Controller.................................................................... 104
Block Diagram of Interrupts IRQ15 to IRQ0 .......................................................... 121
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0. 128
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2. 130
Interrupt Exception Handling .................................................................................. 131
Conflict between Interrupt Generation and Disabling............................................. 134
Block Diagram of Bus Controller............................................................................ 138
Read Strobe Negation Timing (Example of 3-State Access Space) ........................ 150
CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0) ................................................ 152
RAS Signal Assertion Timing (2-State Column Address Output Cycle,
Full Access)............................................................................................................. 163
CAS Latency Control Cycle Disable Timing during Continuous Synchronous
DRAM Space Write Access (for CAS Latency 2) .................................................. 166
Area Divisions......................................................................................................... 171
CSn Signal Output Timing (n = 0 to 7) ................................................................... 176
Access Sizes and Data Alignment Control (8-Bit Access Space) ........................... 177
Access Sizes and Data Alignment Control (16-Bit Access Space) ......................... 177