DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 317

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.9
6.9.1
When this LSI accesses external address space, it can insert an idle cycle (T
in the following three cases: (1) when read accesses in different areas occur consecutively, (2)
when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs
immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the
IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and
so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.65 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
CS (area A)
CS (area B)
Address bus
Idle Cycle
Operation
Data bus
RD
φ
(a) No idle cycle insertion
(ICIS1 = 0)
T
1
Bus cycle A
Long output floating time
Figure 6.65 Example of Idle Cycle Operation
T
2
(Consecutive Reads in Different Areas)
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
RD
Rev.7.00 Mar. 18, 2009 page 249 of 1136
φ
T
1
Bus cycle A
(b) Idle cycle insertion
Section 6 Bus Controller (BSC)
(ICIS1 = 1, initial value)
T
2
T
3
Idle cycle
i
) between bus cycles
T
Bus cycle B
i
REJ09B0109-0700
T
1
T
2