DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 436

IC H8S/2378 MCU FLASH 144-QFP

DF2378BVFQ35WV

Manufacturer Part Number
DF2378BVFQ35WV
Description
IC H8S/2378 MCU FLASH 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2378BVFQ35WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
For Use With
EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2378BVFQ35WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 EXDMA Controller (EXDMAC)
Bit
6
5
4
Rev.7.00 Mar. 18, 2009 page 368 of 1136
REJ09B0109-0700
Bit Name
IRF
TCEIE
SDIR
Initial Value
0
0
0
R/W
R/(W) *
R/W
R/W
Description
Interrupt Request Flag
Flag indicating that an interrupt request has
occurred and transfer has ended.
0: No interrupt request
[Clearing conditions]
1: Interrupt request occurrence
[Setting conditions]
Transfer Counter End Interrupt Enable
Enables or disables transfer end interrupt
requests by the transfer counter. When
transfer ends according to the transfer counter
while this bit is set to 1, the IRF bit is set to 1,
indicating that an interrupt request has
occurred.
0: Transfer end interrupt requests by transfer
1: Transfer end interrupt requests by transfer
Single Address Direction
Specifies the data transfer direction in single
address mode. In dual address mode, the
specification by this bit is ignored.
0: Transfer direction: EDSAR → external
1: Transfer direction: External device with
counter are disabled
counter are enabled
device with DACK
DACK→ EDDAR
Writing 1 to the EDA bit
Writing 0 to IRF after reading IRF = 1
Transfer end interrupt request generated by
transfer counter
Source address repeat area overflow interrupt
request
Destination address repeat area overflow
interrupt request

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