HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 13

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

5.2
5.3
5.4
5.5
Section 6 Interrupt Controller (INTC)
6.1
6.2
6.3
6.4
6.5
Section 7 User Break Controller (UBC)
7.1
5.1.1
5.1.2
5.1.3
Register Description .......................................................................................................... 99
5.2.1
Cache Operation ................................................................................................................ 100
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Memory-Mapped Cache.................................................................................................... 103
5.4.1
5.4.2
Usage Examples ................................................................................................................ 106
5.5.1
5.5.2
Overview............................................................................................................................ 107
6.1.1
6.1.2
6.1.3
6.1.4
Interrupt Sources................................................................................................................ 109
6.2.1
6.2.2
6.2.3
6.2.4
INTC Registers.................................................................................................................. 115
6.3.1
6.3.2
INTC Operation ................................................................................................................. 117
6.4.1
6.4.2
Interrupt Response Time.................................................................................................... 120
Overview............................................................................................................................ 123
7.1.1
7.1.2
7.1.3
Features ................................................................................................................ 97
Cache Structure .................................................................................................... 97
Register Configuration ......................................................................................... 99
Cache Control Register (CCR)............................................................................. 99
Searching the Cache ............................................................................................. 100
Read Access.......................................................................................................... 102
Write Access ........................................................................................................ 102
Write-Back Buffer................................................................................................ 102
Coherency of Cache and External Memory ......................................................... 103
RAM Mode .......................................................................................................... 103
Address Array ...................................................................................................... 103
Data Array ............................................................................................................ 104
Invalidating Specific Entries ................................................................................ 106
Reading the Data of a Specific Entry ................................................................... 106
Features ................................................................................................................ 107
Block Diagram...................................................................................................... 108
Pin Configuration ................................................................................................. 109
Register Configuration ......................................................................................... 109
NMI Interrupts...................................................................................................... 110
IRL Interrupts ....................................................................................................... 110
On-Chip Supporting Module Interrupts ............................................................... 112
Interrupt Exception Handling and Priority ........................................................... 112
Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 115
Interrupt Control Register (ICR) .......................................................................... 116
Interrupt Sequence................................................................................................ 117
Multiple Interrupts................................................................................................ 119
Features ................................................................................................................ 123
Block Diagram...................................................................................................... 123
Register Configuration ......................................................................................... 125
........................................................................... 107
........................................................................ 123
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