HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 317

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

IRQOUT Pin Assertion Conditions:
10.4
10.4.1
Note the following concerning the SH7708 (not including the SH7708S and SH7708R).
When SDRAM, DRAM, or PSRAM is connected, cases such as the following can be envisaged in
which the contents of register BCR2, which sets the bus width of each area, and the MCR.SZ bits,
which set the bus width of SDRAM, DRAM, and PSRAM, are different.
In these cases, one of the following settings should be made.
10.4.2
Note the following concerning the SH7708 Series (SH7708, SH7708S, SH7708R).
When a memory refresh request has been generated but the refresh cycle has not yet begun
When an interrupt is generated with an interrupt request level higher than the setting of the
interrupt mask bits (I3–I0) in the status register (SR). (This does not depend on the SR.BL bit.)
A setting other than 32 bits in the BCR2 register and MCR register when SDRAM is
connected
A setting of 16 bits in the BCR2 register and 32 bits in the MCR register when DRAM is
connected in area 3 only
A setting of 32 bits in the BCR2 register and 16 bits in the MCR register when DRAM is
connected in area 3 only
A setting other than 16 bits in the BCR2 register and MCR register when DRAM is connected
in areas 2 and 3
Different bus width settings in the BCR register and MCR register when PSRAM is connected
When SDRAM is connected, use a 32-bit bus width setting in the BCR2 register and MCR
register.
When DRAM is connected in area 3 only, use the same bus width setting (16 or 32 bits) in the
BCR2 register and MCR register.
When DRAM is connected in areas 2 and 3, use a 16-bit bus width setting in the BCR2 register
and MCR register.
When PSRAM is connected, use the same bus width setting (16 or 32 bits) in the BCR2
register and MCR register.
Usage Notes
Area 2 and 3 Bus Width Setting
When Area 6 is Designated for PCMCIA, with a 16-Bit Bus Width
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