HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 148
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Bits 1 and 0—Break Address Mask A1 and A0 (BAMA1 and BAMA0): These bits indicate which
of the channel A break address bits 31–0 (BAA31–BAA0) set in BARA are masked.
Bit 1: BAMA1
0
0
1
1
7.2.6
BAMRB is the break address mask register for channel B. The bit configuration is the same as for
BAMRA.
7.2.7
The break bus cycle register A (BBRA) is a 16-bit read/write register that sets the following three
channel A break conditions for channel A: (1) instruction fetch/data access, (2) read/write, and (3)
operand size. A reset initializes BBRA to H'0000.
Bits 15 to 6—Reserved: These bits always read 0. The write value should always be 0.
128
Initial value:
Initial value:
Bit name:
Bit name:
Break Address Mask Register B (BAMRB)
Break Bus Cycle Register A (BBRA)
R/W:
R/W:
Bit:
Bit:
Bit 0: BAMA0
0
1
0
1
15
—
—
0
R
7
0
R
14
—
—
0
R
6
0
R
Description
BARA not masked; all bits included in break condition.
Lowest 10 bits masked and excluded from break condition.
Lowest 12 bits masked and excluded from break condition.
All BARA bits masked; address not included in break
condition.
IDA1
R/W
13
—
0
R
5
0
IDA0
R/W
12
—
0
R
4
0
RWA1
R/W
11
—
0
R
3
0
RWA0
R/W
10
—
0
R
2
0
SZA1
R/W
—
9
0
R
1
0
SZA0
R/W
—
8
0
R
0
0
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