HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 367
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
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Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
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Quantity:
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Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous
mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because
no stop bits are added.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP
0
1
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is
selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit
setting is used only in asynchronous mode; it is ignored in synchronous mode. For the
multiprocessor communication function, see section 13.3.3, Multiprocessor Communication.
Bit 2: MP
0
1
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock source
of the on-chip baud rate generator. Four clock sources are available: P , P /4, P /16 and P /64.
For further information on the clock source, bit rate register settings, and baud rate, see section
13.2.9, Bit Rate Register.
Bit 1: CKS1
0
1
Note: P : Peripheral clock
Bit 0: CKS0
0
1
0
1
Description
One stop bit
In transmitting, a single 1-bit is added at the end of each transmitted
character.
Two stop bits
In transmitting, two 1-bits are added at the end of each transmitted
character.
Description
Multiprocessor function disabled
Multiprocessor format selected
Description
P
P /4
P /16
P /64
(Initial value)
(Initial value)
(Initial value)
347
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