HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 62

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Table 2.11 System Control Instructions (cont)
Instruction
LDC.L @Rm+,
LDC.L @Rm+,
LDC.L @Rm+,
LDC.L @Rm+,
LDS
LDS
LDS
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
LDTLB
NOP
PREF
RTE
SETS
SETT
SLEEP
STC
STC
STC
STC
STC
STC
STC
STC
STC
Note: * The number of cycles until the sleep state is entered.
42
R4_BANK
R5_BANK
R6_BANK
R7_BANK
Rm,MACH
Rm,MACL
Rm,PR
@Rm
SR,Rn
GBR,Rn
VBR,Rn
SSR,Rn
SPC,Rn
R0_BANK,Rn
R1_BANK,Rn
R2_BANK,Rn
R3_BANK,Rn
Operation
(Rm)
Rm + 4
(Rm)
Rm + 4
(Rm)
Rm + 4
(Rm)
Rm + 4
Rm
Rm
Rm
(Rm)
(Rm)
(Rm)
PTEH/PTEL
No operation
(Rm)
Delayed branch,
SSR/SPC
1
1
Sleep
SR
GBR
VBR
SSR
SPC
R0_BANK
R1_BANK
R2_BANK
R3_BANK
S
T
Rn
MACH
MACL
PR
Rn
Rn
Rn
R4_BANK,
R5_BANK,
R6_BANK,
R7_BANK,
MACH, Rm + 4
MACL, Rm + 4
PR, Rm + 4
cache
Rn
Rm
Rm
Rm
Rm
Rn
Rn
Rn
Rn
SR/PC
TLB
Rm
Rm
Rm
Code
0100mmmm11000111
0100mmmm11010111
0100mmmm11100111
0100mmmm11110111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000111000
0000000000001001
0000mmmm10000011
0000000000101011
0000000001011000
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0000nnnn00110010
0000nnnn01000010
0000nnnn10000010
0000nnnn10010010
0000nnnn10100010
0000nnnn10110010
Privileged
Mode
—
—
—
—
—
—
—
—
—
—
—
Cycles T Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
4
1
1
4*
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—